1/* 2 * Copyright (c) 2010-2012 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 705 unchanged lines hidden (view full) --- 714TimingSimpleCPU::IcachePort::ITickEvent::process() 715{ 716 cpu->completeIfetch(pkt); 717} 718 719bool 720TimingSimpleCPU::IcachePort::recvTimingResp(PacketPtr pkt) 721{ |
722 DPRINTF(SimpleCPU, "Received timing response %#x\n", pkt->getAddr()); 723 // delay processing of returned data until next CPU clock edge 724 Tick next_tick = cpu->nextCycle(); |
725 |
726 if (next_tick == curTick()) 727 cpu->completeIfetch(pkt); 728 else 729 tickEvent.schedule(pkt, next_tick); |
730 |
731 return true; 732} 733 734void 735TimingSimpleCPU::IcachePort::recvRetry() 736{ 737 // we shouldn't get a retry unless we have a packet that we're 738 // waiting to transmit --- 84 unchanged lines hidden (view full) --- 823 DPRINTF(Drain, "CPU done draining, processing drain event\n"); 824 changeState(SimObject::Drained); 825 drainEvent->process(); 826} 827 828bool 829TimingSimpleCPU::DcachePort::recvTimingResp(PacketPtr pkt) 830{ |
831 // delay processing of returned data until next CPU clock edge 832 Tick next_tick = cpu->nextCycle(); |
833 |
834 if (next_tick == curTick()) { 835 cpu->completeDataAccess(pkt); 836 } else { 837 if (!tickEvent.scheduled()) { 838 tickEvent.schedule(pkt, next_tick); |
839 } else { |
840 // In the case of a split transaction and a cache that is 841 // faster than a CPU we could get two responses before 842 // next_tick expires 843 if (!retryEvent.scheduled()) 844 cpu->schedule(retryEvent, next_tick); 845 return false; |
846 } |
847 } 848 849 return true; 850} 851 852void 853TimingSimpleCPU::DcachePort::DTickEvent::process() 854{ --- 86 unchanged lines hidden --- |