1/*
2 * Copyright (c) 2010-2012 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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43#include "arch/locked_mem.hh"
44#include "arch/mmapped_ipr.hh"
45#include "arch/utility.hh"
46#include "base/bigint.hh"
47#include "config/the_isa.hh"
48#include "cpu/simple/timing.hh"
49#include "cpu/exetrace.hh"
50#include "debug/Config.hh"
51#include "debug/Drain.hh"
52#include "debug/ExecFaulting.hh"
53#include "debug/SimpleCPU.hh"
54#include "mem/packet.hh"
55#include "mem/packet_access.hh"
56#include "params/TimingSimpleCPU.hh"
57#include "sim/faults.hh"
58#include "sim/full_system.hh"
59#include "sim/system.hh"

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125 // TimingSimpleCPU is ready to drain if it's not waiting for
126 // an access to complete.
127 if (_status == Idle || _status == Running || _status == SwitchedOut) {
128 changeState(SimObject::Drained);
129 return 0;
130 } else {
131 changeState(SimObject::Draining);
132 drainEvent = drain_event;
133 DPRINTF(Drain, "CPU not drained\n");
134 return 1;
135 }
136}
137
138void
139TimingSimpleCPU::resume()
140{
141 DPRINTF(SimpleCPU, "Resume\n");

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826
827 advanceInst(fault);
828}
829
830
831void
832TimingSimpleCPU::completeDrain()
833{
832 DPRINTF(Config, "Done draining\n");
834 DPRINTF(Drain, "CPU done draining, processing drain event\n");
835 changeState(SimObject::Drained);
836 drainEvent->process();
837}
838
839bool
840TimingSimpleCPU::DcachePort::recvTimingResp(PacketPtr pkt)
841{
842 if (!pkt->wasNacked()) {

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