1/* 2 * Copyright (c) 2010 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 371 unchanged lines hidden (view full) --- 380 if (req->getFlags().isSet(Request::NO_ACCESS)) { 381 buildPacket(pkt1, req, read); 382 return; 383 } 384 385 buildPacket(pkt1, req1, read); 386 buildPacket(pkt2, req2, read); 387 |
388 req->setPhys(req1->getPaddr(), req->getSize(), req1->getFlags(), dataMasterId()); |
389 PacketPtr pkt = new Packet(req, pkt1->cmd.responseCommand(), 390 Packet::Broadcast); 391 392 pkt->dataDynamicArray<uint8_t>(data); 393 pkt1->dataStatic<uint8_t>(data); 394 pkt2->dataStatic<uint8_t>(data + req1->getSize()); 395 396 SplitMainSenderState * main_send_state = new SplitMainSenderState; --- 16 unchanged lines hidden (view full) --- 413 unsigned block_size = dcachePort.peerBlockSize(); 414 BaseTLB::Mode mode = BaseTLB::Read; 415 416 if (traceData) { 417 traceData->setAddr(addr); 418 } 419 420 RequestPtr req = new Request(asid, addr, size, |
421 flags, dataMasterId(), pc, _cpuId, tid); |
422 423 Addr split_addr = roundDown(addr + size - 1, block_size); 424 assert(split_addr <= addr || split_addr - addr < block_size); 425 426 _status = DTBWaitResponse; 427 if (split_addr > addr) { 428 RequestPtr req1, req2; 429 assert(!req->isLLSC() && !req->isSwap()); --- 53 unchanged lines hidden (view full) --- 483 unsigned block_size = dcachePort.peerBlockSize(); 484 BaseTLB::Mode mode = BaseTLB::Write; 485 486 if (traceData) { 487 traceData->setAddr(addr); 488 } 489 490 RequestPtr req = new Request(asid, addr, size, |
491 flags, dataMasterId(), pc, _cpuId, tid); |
492 493 Addr split_addr = roundDown(addr + size - 1, block_size); 494 assert(split_addr <= addr || split_addr - addr < block_size); 495 496 _status = DTBWaitResponse; 497 if (split_addr > addr) { 498 RequestPtr req1, req2; 499 assert(!req->isLLSC() && !req->isSwap()); --- 473 unchanged lines hidden --- |