1/* 2 * Copyright (c) 2010 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software
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474 DataTranslation<TimingSimpleCPU> *translation 475 = new DataTranslation<TimingSimpleCPU>(this, state); 476 thread->dtb->translateTiming(req, tc, translation, mode); 477 } 478 479 return NoFault; 480} 481
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482template <class T>
483Fault
484TimingSimpleCPU::read(Addr addr, T &data, unsigned flags)
485{
486 return readBytes(addr, (uint8_t *)&data, sizeof(T), flags);
487}
488
489#ifndef DOXYGEN_SHOULD_SKIP_THIS
490
491template
492Fault
493TimingSimpleCPU::read(Addr addr, Twin64_t &data, unsigned flags);
494
495template
496Fault
497TimingSimpleCPU::read(Addr addr, Twin32_t &data, unsigned flags);
498
499template
500Fault
501TimingSimpleCPU::read(Addr addr, uint64_t &data, unsigned flags);
502
503template
504Fault
505TimingSimpleCPU::read(Addr addr, uint32_t &data, unsigned flags);
506
507template
508Fault
509TimingSimpleCPU::read(Addr addr, uint16_t &data, unsigned flags);
510
511template
512Fault
513TimingSimpleCPU::read(Addr addr, uint8_t &data, unsigned flags);
514
515#endif //DOXYGEN_SHOULD_SKIP_THIS
516
517template<>
518Fault
519TimingSimpleCPU::read(Addr addr, double &data, unsigned flags)
520{
521 return read(addr, *(uint64_t*)&data, flags);
522}
523
524template<>
525Fault
526TimingSimpleCPU::read(Addr addr, float &data, unsigned flags)
527{
528 return read(addr, *(uint32_t*)&data, flags);
529}
530
531template<>
532Fault
533TimingSimpleCPU::read(Addr addr, int32_t &data, unsigned flags)
534{
535 return read(addr, (uint32_t&)data, flags);
536}
537
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482bool 483TimingSimpleCPU::handleWritePacket() 484{ 485 RequestPtr req = dcache_pkt->req; 486 if (req->isMmappedIpr()) { 487 Tick delay; 488 delay = TheISA::handleIprWrite(thread->getTC(), dcache_pkt); 489 new IprEvent(dcache_pkt, this, nextCycle(curTick() + delay));
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495 _status = DcacheWaitResponse; 496 // memory system takes ownership of packet 497 dcache_pkt = NULL; 498 } 499 return dcache_pkt == NULL; 500} 501 502Fault
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559TimingSimpleCPU::writeTheseBytes(uint8_t *data, unsigned size,
560 Addr addr, unsigned flags, uint64_t *res)
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503TimingSimpleCPU::writeBytes(uint8_t *data, unsigned size, 504 Addr addr, unsigned flags, uint64_t *res) |
505{
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506 uint8_t *newData = new uint8_t[size]; 507 memcpy(newData, data, size); 508 |
509 const int asid = 0; 510 const ThreadID tid = 0; 511 const Addr pc = thread->instAddr(); 512 unsigned block_size = dcachePort.peerBlockSize(); 513 BaseTLB::Mode mode = BaseTLB::Write; 514 515 if (traceData) { 516 traceData->setAddr(addr);
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524 525 _status = DTBWaitResponse; 526 if (split_addr > addr) { 527 RequestPtr req1, req2; 528 assert(!req->isLLSC() && !req->isSwap()); 529 req->splitOnVaddr(split_addr, req1, req2); 530 531 WholeTranslationState *state =
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585 new WholeTranslationState(req, req1, req2, data, res, mode);
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532 new WholeTranslationState(req, req1, req2, newData, res, mode); |
533 DataTranslation<TimingSimpleCPU> *trans1 = 534 new DataTranslation<TimingSimpleCPU>(this, state, 0); 535 DataTranslation<TimingSimpleCPU> *trans2 = 536 new DataTranslation<TimingSimpleCPU>(this, state, 1); 537 538 thread->dtb->translateTiming(req1, tc, trans1, mode); 539 thread->dtb->translateTiming(req2, tc, trans2, mode); 540 } else { 541 WholeTranslationState *state =
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595 new WholeTranslationState(req, data, res, mode);
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542 new WholeTranslationState(req, newData, res, mode); |
543 DataTranslation<TimingSimpleCPU> *translation = 544 new DataTranslation<TimingSimpleCPU>(this, state); 545 thread->dtb->translateTiming(req, tc, translation, mode); 546 } 547 548 // Translation faults will be returned via finishTranslation() 549 return NoFault; 550} 551
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605Fault
606TimingSimpleCPU::writeBytes(uint8_t *data, unsigned size,
607 Addr addr, unsigned flags, uint64_t *res)
608{
609 uint8_t *newData = new uint8_t[size];
610 memcpy(newData, data, size);
611 return writeTheseBytes(newData, size, addr, flags, res);
612}
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552
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614template <class T>
615Fault
616TimingSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res)
617{
618 if (traceData) {
619 traceData->setData(data);
620 }
621 T *dataP = (T*) new uint8_t[sizeof(T)];
622 *dataP = TheISA::htog(data);
623
624 return writeTheseBytes((uint8_t *)dataP, sizeof(T), addr, flags, res);
625}
626
627
628#ifndef DOXYGEN_SHOULD_SKIP_THIS
629template
630Fault
631TimingSimpleCPU::write(Twin32_t data, Addr addr,
632 unsigned flags, uint64_t *res);
633
634template
635Fault
636TimingSimpleCPU::write(Twin64_t data, Addr addr,
637 unsigned flags, uint64_t *res);
638
639template
640Fault
641TimingSimpleCPU::write(uint64_t data, Addr addr,
642 unsigned flags, uint64_t *res);
643
644template
645Fault
646TimingSimpleCPU::write(uint32_t data, Addr addr,
647 unsigned flags, uint64_t *res);
648
649template
650Fault
651TimingSimpleCPU::write(uint16_t data, Addr addr,
652 unsigned flags, uint64_t *res);
653
654template
655Fault
656TimingSimpleCPU::write(uint8_t data, Addr addr,
657 unsigned flags, uint64_t *res);
658
659#endif //DOXYGEN_SHOULD_SKIP_THIS
660
661template<>
662Fault
663TimingSimpleCPU::write(double data, Addr addr, unsigned flags, uint64_t *res)
664{
665 return write(*(uint64_t*)&data, addr, flags, res);
666}
667
668template<>
669Fault
670TimingSimpleCPU::write(float data, Addr addr, unsigned flags, uint64_t *res)
671{
672 return write(*(uint32_t*)&data, addr, flags, res);
673}
674
675
676template<>
677Fault
678TimingSimpleCPU::write(int32_t data, Addr addr, unsigned flags, uint64_t *res)
679{
680 return write((uint32_t)data, addr, flags, res);
681}
682
683
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553void 554TimingSimpleCPU::finishTranslation(WholeTranslationState *state) 555{ 556 _status = Running; 557 558 if (state->getFault() != NoFault) { 559 if (state->isPrefetch()) { 560 state->setNoFault();
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