1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 854 unchanged lines hidden (view full) ---

863}
864
865void
866TimingSimpleCPU::completeDataAccess(PacketPtr pkt)
867{
868 // received a response from the dcache: complete the load or store
869 // instruction
870 assert(!pkt->isError());
871 assert(_status == DcacheWaitResponse || _status == DTBWaitResponse ||
872 pkt->req->getFlags().isSet(Request::NO_ACCESS));
873
874 numCycles += tickToCycles(curTick - previousTick);
875 previousTick = curTick;
876
877 if (pkt->senderState) {
878 SplitFragmentSenderState * send_state =
879 dynamic_cast<SplitFragmentSenderState *>(pkt->senderState);
880 assert(send_state);

--- 13 unchanged lines hidden (view full) ---

894 return;
895 } else {
896 delete main_send_state;
897 big_pkt->senderState = NULL;
898 pkt = big_pkt;
899 }
900 }
901
900 assert(_status == DcacheWaitResponse || _status == DTBWaitResponse);
902 _status = Running;
903
904 Fault fault = curStaticInst->completeAcc(pkt, this, traceData);
905
906 // keep an instruction count
907 if (fault == NoFault)
908 countInst();
909 else if (traceData) {

--- 165 unchanged lines hidden ---