1/* 2 * Copyright (c) 2002-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 517 unchanged lines hidden (view full) --- 526{ 527 DPRINTF(SimpleCPU, "Fetch\n"); 528 529 if (!curStaticInst || !curStaticInst->isDelayedCommit()) 530 checkForInterrupts(); 531 532 checkPcEventQueue(); 533 |
534 bool fromRom = isRomMicroPC(thread->readMicroPC()); |
535 |
536 if (!fromRom) { 537 Request *ifetch_req = new Request(); 538 ifetch_req->setThreadContext(cpuId, /* thread ID */ 0); 539 Fault fault = setupFetchRequest(ifetch_req); |
540 |
541 ifetch_pkt = new Packet(ifetch_req, MemCmd::ReadReq, Packet::Broadcast); 542 ifetch_pkt->dataStatic(&inst); 543 544 if (fault == NoFault) { 545 if (!icachePort.sendTiming(ifetch_pkt)) { 546 // Need to wait for retry 547 _status = IcacheRetry; 548 } else { 549 // Need to wait for cache to respond 550 _status = IcacheWaitResponse; 551 // ownership of packet transferred to memory system 552 ifetch_pkt = NULL; 553 } |
554 } else { |
555 delete ifetch_req; 556 delete ifetch_pkt; 557 // fetch fault: advance directly to next instruction (fault handler) 558 advanceInst(fault); |
559 } 560 } else { |
561 _status = IcacheWaitResponse; 562 completeIfetch(NULL); |
563 } 564 565 numCycles += tickToCycles(curTick - previousTick); 566 previousTick = curTick; 567} 568 569 570void --- 12 unchanged lines hidden (view full) --- 583 584void 585TimingSimpleCPU::completeIfetch(PacketPtr pkt) 586{ 587 DPRINTF(SimpleCPU, "Complete ICache Fetch\n"); 588 589 // received a response from the icache: execute the received 590 // instruction |
591 592 assert(!pkt || !pkt->isError()); |
593 assert(_status == IcacheWaitResponse); 594 595 _status = Running; 596 597 numCycles += tickToCycles(curTick - previousTick); 598 previousTick = curTick; 599 600 if (getState() == SimObject::Draining) { |
601 if (pkt) { 602 delete pkt->req; 603 delete pkt; 604 } |
605 606 completeDrain(); 607 return; 608 } 609 610 preExecute(); 611 if (curStaticInst->isMemRef() && !curStaticInst->isDataPrefetch()) { 612 // load or store: just send to dcache --- 50 unchanged lines hidden (view full) --- 663 postExecute(); 664 // @todo remove me after debugging with legion done 665 if (curStaticInst && (!curStaticInst->isMicroop() || 666 curStaticInst->isFirstMicroop())) 667 instCnt++; 668 advanceInst(fault); 669 } 670 |
671 if (pkt) { 672 delete pkt->req; 673 delete pkt; 674 } |
675} 676 677void 678TimingSimpleCPU::IcachePort::ITickEvent::process() 679{ 680 cpu->completeIfetch(pkt); 681} 682 --- 193 unchanged lines hidden --- |