1/* 2 * Copyright (c) 2002-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 282 unchanged lines hidden (view full) --- 291 292 // This will need a new way to tell if it has a dcache attached. 293 if (req->isUncacheable()) 294 recordEvent("Uncached Read"); 295 } else { 296 delete req; 297 } 298 |
299 if (traceData) { 300 traceData->setData(data); 301 } |
302 return fault; 303} 304 305Fault 306TimingSimpleCPU::translateDataReadAddr(Addr vaddr, Addr &paddr, 307 int size, unsigned flags) 308{ 309 Request *req = --- 119 unchanged lines hidden (view full) --- 429 } 430 // This will need a new way to tell if it's hooked up to a cache or not. 431 if (req->isUncacheable()) 432 recordEvent("Uncached Write"); 433 } else { 434 delete req; 435 } 436 |
437 if (traceData) { 438 traceData->setData(data); 439 } |
440 441 // If the write needs to have a fault on the access, consider calling 442 // changeStatus() and changing it to "bad addr write" or something. 443 return fault; 444} 445 446Fault 447TimingSimpleCPU::translateDataWriteAddr(Addr vaddr, Addr &paddr, --- 438 unchanged lines hidden --- |