1/* 2 * Copyright (c) 2002-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 143 unchanged lines hidden (view full) --- 152 drainEvent = drain_event; 153 return 1; 154 } 155} 156 157void 158TimingSimpleCPU::resume() 159{ |
160 DPRINTF(SimpleCPU, "Resume\n"); |
161 if (_status != SwitchedOut && _status != Idle) { 162 assert(system->getMemoryMode() == Enums::timing); 163 164 // Delete the old event if it existed. 165 if (fetchEvent) { 166 if (fetchEvent->scheduled()) 167 fetchEvent->deschedule(); 168 --- 42 unchanged lines hidden (view full) --- 211 cpuId = tc->readCpuId(); 212 previousTick = curTick; 213} 214 215 216void 217TimingSimpleCPU::activateContext(int thread_num, int delay) 218{ |
219 DPRINTF(SimpleCPU, "ActivateContext %d (%d cycles)\n", thread_num, delay); 220 |
221 assert(thread_num == 0); 222 assert(thread); 223 224 assert(_status == Idle); 225 226 notIdleFraction++; 227 _status = Running; 228 229 // kick things off by initiating the fetch of the next instruction 230 fetchEvent = new FetchEvent(this, nextCycle(curTick + ticks(delay))); 231} 232 233 234void 235TimingSimpleCPU::suspendContext(int thread_num) 236{ |
237 DPRINTF(SimpleCPU, "SuspendContext %d\n", thread_num); 238 |
239 assert(thread_num == 0); 240 assert(thread); 241 242 assert(_status == Running); 243 244 // just change status to Idle... if status != Running, 245 // completeInst() will not initiate fetch of next instruction. 246 --- 264 unchanged lines hidden (view full) --- 511{ 512 return write((uint32_t)data, addr, flags, res); 513} 514 515 516void 517TimingSimpleCPU::fetch() 518{ |
519 DPRINTF(SimpleCPU, "Fetch\n"); 520 |
521 if (!curStaticInst || !curStaticInst->isDelayedCommit()) 522 checkForInterrupts(); 523 524 Request *ifetch_req = new Request(); 525 ifetch_req->setThreadContext(cpuId, /* thread ID */ 0); 526 Fault fault = setupFetchRequest(ifetch_req); 527 528 ifetch_pkt = new Packet(ifetch_req, MemCmd::ReadReq, Packet::Broadcast); --- 33 unchanged lines hidden (view full) --- 562 fetch(); 563 } 564} 565 566 567void 568TimingSimpleCPU::completeIfetch(PacketPtr pkt) 569{ |
570 DPRINTF(SimpleCPU, "Complete ICache Fetch\n"); 571 |
572 // received a response from the icache: execute the received 573 // instruction 574 assert(!pkt->isError()); 575 assert(_status == IcacheWaitResponse); 576 577 _status = Running; 578 579 numCycles += tickToCycles(curTick - previousTick); --- 284 unchanged lines hidden --- |