1/* 2 * Copyright (c) 2002-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 342 unchanged lines hidden (view full) --- 351 // translate to physical address 352 Fault fault = thread->translateDataWriteReq(req); 353 354 // Now do the access. 355 if (fault == NoFault) { 356 MemCmd cmd = MemCmd::WriteReq; // default 357 bool do_access = true; // flag to suppress cache access 358 |
359 if (req->isLocked()) { 360 cmd = MemCmd::StoreCondReq; 361 do_access = TheISA::handleLockedWrite(thread, req); 362 } else if (req->isSwap()) { 363 cmd = MemCmd::SwapReq; 364 if (req->isCondSwap()) { 365 assert(res); 366 req->setExtraData(*res); 367 } 368 } 369 |
370 // Note: need to allocate dcache_pkt even if do_access is 371 // false, as it's used unconditionally to call completeAcc(). 372 assert(dcache_pkt == NULL); 373 dcache_pkt = new Packet(req, cmd, Packet::Broadcast); 374 dcache_pkt->allocate(); 375 dcache_pkt->set(data); |
376 |
377 if (do_access) { |
378 if (!dcachePort.sendTiming(dcache_pkt)) { 379 _status = DcacheRetry; 380 } else { 381 _status = DcacheWaitResponse; 382 // memory system takes ownership of packet 383 dcache_pkt = NULL; 384 } 385 } --- 428 unchanged lines hidden --- |