1/* 2 * Copyright (c) 2002-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 546 unchanged lines hidden (view full) --- 555 cpu->completeIfetch(pkt); 556} 557 558bool 559TimingSimpleCPU::IcachePort::recvTiming(PacketPtr pkt) 560{ 561 if (pkt->isResponse()) { 562 // delay processing of returned data until next CPU clock edge |
563 Tick next_tick = cpu->nextCycle(curTick); |
564 565 if (next_tick == curTick) 566 cpu->completeIfetch(pkt); 567 else 568 tickEvent.schedule(pkt, next_tick); 569 570 return true; 571 } --- 77 unchanged lines hidden (view full) --- 649#endif 650} 651 652bool 653TimingSimpleCPU::DcachePort::recvTiming(PacketPtr pkt) 654{ 655 if (pkt->isResponse()) { 656 // delay processing of returned data until next CPU clock edge |
657 Tick next_tick = cpu->nextCycle(curTick); |
658 659 if (next_tick == curTick) 660 cpu->completeDataAccess(pkt); 661 else 662 tickEvent.schedule(pkt, next_tick); 663 664 return true; 665 } --- 142 unchanged lines hidden --- |