1/* 2 * Copyright (c) 2002-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 45 unchanged lines hidden (view full) --- 54void 55TimingSimpleCPU::init() 56{ 57 BaseCPU::init(); 58#if FULL_SYSTEM 59 for (int i = 0; i < threadContexts.size(); ++i) { 60 ThreadContext *tc = threadContexts[i]; 61 |
62 // initialize CPU, including PC 63 TheISA::initCPU(tc, tc->readCpuId()); 64 } 65#endif 66} 67 68Tick 69TimingSimpleCPU::CpuPort::recvAtomic(PacketPtr pkt) --- 163 unchanged lines hidden (view full) --- 233{ 234 assert(thread_num == 0); 235 assert(thread); 236 237 assert(_status == Idle); 238 239 notIdleFraction++; 240 _status = Running; |
241 242#if FULL_SYSTEM 243 // Connect the ThreadContext's memory ports (Functional/Virtual 244 // Ports) 245 tc->connectMemPorts(); 246#endif 247 |
248 // kick things off by initiating the fetch of the next instruction 249 fetchEvent = 250 new EventWrapper<TimingSimpleCPU, &TimingSimpleCPU::fetch>(this, false); 251 fetchEvent->schedule(nextCycle(curTick + cycles(delay))); 252} 253 254 255void --- 527 unchanged lines hidden --- |