1/* 2 * Copyright (c) 2002-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 276 unchanged lines hidden (view full) --- 285 if (!dcachePort.sendTiming(pkt)) { 286 _status = DcacheRetry; 287 dcache_pkt = pkt; 288 } else { 289 _status = DcacheWaitResponse; 290 // memory system takes ownership of packet 291 dcache_pkt = NULL; 292 } |
293 } else { 294 delete req; |
295 } 296 297 // This will need a new way to tell if it has a dcache attached. 298 if (req->isUncacheable()) 299 recordEvent("Uncached Read"); 300 301 return fault; 302} --- 69 unchanged lines hidden (view full) --- 372 if (!dcachePort.sendTiming(dcache_pkt)) { 373 _status = DcacheRetry; 374 } else { 375 _status = DcacheWaitResponse; 376 // memory system takes ownership of packet 377 dcache_pkt = NULL; 378 } 379 } |
380 } else { 381 delete req; |
382 } 383 384 // This will need a new way to tell if it's hooked up to a cache or not. 385 if (req->isUncacheable()) 386 recordEvent("Uncached Write"); 387 388 // If the write needs to have a fault on the access, consider calling 389 // changeStatus() and changing it to "bad addr write" or something. --- 66 unchanged lines hidden (view full) --- 456 _status = IcacheRetry; 457 } else { 458 // Need to wait for cache to respond 459 _status = IcacheWaitResponse; 460 // ownership of packet transferred to memory system 461 ifetch_pkt = NULL; 462 } 463 } else { |
464 delete ifetch_req; 465 delete ifetch_pkt; |
466 // fetch fault: advance directly to next instruction (fault handler) 467 advanceInst(fault); 468 } 469 470 numCycles += curTick - previousTick; 471 previousTick = curTick; 472} 473 --- 17 unchanged lines hidden (view full) --- 491{ 492 // received a response from the icache: execute the received 493 // instruction 494 assert(pkt->result == Packet::Success); 495 assert(_status == IcacheWaitResponse); 496 497 _status = Running; 498 |
499 numCycles += curTick - previousTick; 500 previousTick = curTick; 501 502 if (getState() == SimObject::Draining) { |
503 delete pkt->req; 504 delete pkt; 505 |
506 completeDrain(); 507 return; 508 } 509 510 preExecute(); 511 if (curStaticInst->isMemRef() && !curStaticInst->isDataPrefetch()) { 512 // load or store: just send to dcache 513 Fault fault = curStaticInst->initiateAcc(this, traceData); --- 15 unchanged lines hidden (view full) --- 529 advanceInst(fault); 530 } 531 } else { 532 // non-memory instruction: execute completely now 533 Fault fault = curStaticInst->execute(this, traceData); 534 postExecute(); 535 advanceInst(fault); 536 } |
537 538 delete pkt->req; 539 delete pkt; |
540} 541 542void 543TimingSimpleCPU::IcachePort::ITickEvent::process() 544{ 545 cpu->completeIfetch(pkt); 546} 547 --- 228 unchanged lines hidden --- |