1/* 2 * Copyright (c) 2002-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 514 unchanged lines hidden (view full) --- 523TimingSimpleCPU::IcachePort::ITickEvent::process() 524{ 525 cpu->completeIfetch(pkt); 526} 527 528bool 529TimingSimpleCPU::IcachePort::recvTiming(Packet *pkt) 530{ |
531 if (pkt->isResponse()) { 532 // delay processing of returned data until next CPU clock edge 533 Tick time = pkt->req->getTime(); 534 while (time < curTick) 535 time += lat; |
536 |
537 if (time == curTick) 538 cpu->completeIfetch(pkt); 539 else 540 tickEvent.schedule(pkt, time); |
541 |
542 return true; 543 } 544 else { 545 //Snooping a Coherence Request, do nothing 546 return true; 547 } |
548} 549 550void 551TimingSimpleCPU::IcachePort::recvRetry() 552{ 553 // we shouldn't get a retry unless we have a packet that we're 554 // waiting to transmit 555 assert(cpu->ifetch_pkt != NULL); --- 45 unchanged lines hidden (view full) --- 601 DPRINTF(Config, "Done draining\n"); 602 changeState(SimObject::Drained); 603 drainEvent->process(); 604} 605 606bool 607TimingSimpleCPU::DcachePort::recvTiming(Packet *pkt) 608{ |
609 if (pkt->isResponse()) { 610 // delay processing of returned data until next CPU clock edge 611 Tick time = pkt->req->getTime(); 612 while (time < curTick) 613 time += lat; |
614 |
615 if (time == curTick) 616 cpu->completeDataAccess(pkt); 617 else 618 tickEvent.schedule(pkt, time); |
619 |
620 return true; 621 } 622 else { 623 //Snooping a coherence req, do nothing 624 return true; 625 } |
626} 627 628void 629TimingSimpleCPU::DcachePort::DTickEvent::process() 630{ 631 cpu->completeDataAccess(pkt); 632} 633 --- 114 unchanged lines hidden --- |