1/* 2 * Copyright (c) 2002-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 213 unchanged lines hidden (view full) --- 222 _status = Idle; 223} 224 225 226template <class T> 227Fault 228TimingSimpleCPU::read(Addr addr, T &data, unsigned flags) 229{ |
230 Request *req = 231 new Request(/* asid */ 0, addr, sizeof(T), flags, thread->readPC(), 232 /* CPU ID */ 0, /* thread ID */ 0); |
233 234 if (traceData) { |
235 traceData->setAddr(req->getVaddr()); |
236 } 237 238 // translate to physical address |
239 Fault fault = thread->translateDataReadReq(req); |
240 241 // Now do the access. 242 if (fault == NoFault) { |
243 Packet *pkt = 244 new Packet(req, Packet::ReadReq, Packet::Broadcast); 245 pkt->dataDynamic |
246 |
247 if (!dcachePort.sendTiming(pkt)) { |
248 _status = DcacheRetry; |
249 dcache_pkt = pkt; |
250 } else { 251 _status = DcacheWaitResponse; |
252 // memory system takes ownership of packet |
253 dcache_pkt = NULL; 254 } 255 } 256 257 // This will need a new way to tell if it has a dcache attached. |
258 if (req->getFlags() & UNCACHEABLE) |
259 recordEvent("Uncached Read"); 260 261 return fault; 262} 263 264#ifndef DOXYGEN_SHOULD_SKIP_THIS 265 266template --- 36 unchanged lines hidden (view full) --- 303 return read(addr, (uint32_t&)data, flags); 304} 305 306 307template <class T> 308Fault 309TimingSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res) 310{ |
311 Request *req = 312 new Request(/* asid */ 0, addr, sizeof(T), flags, thread->readPC(), 313 /* CPU ID */ 0, /* thread ID */ 0); |
314 315 // translate to physical address |
316 Fault fault = thread->translateDataWriteReq(req); 317 |
318 // Now do the access. 319 if (fault == NoFault) { |
320 assert(dcache_pkt == NULL); 321 dcache_pkt = new Packet(req, Packet::WriteReq, Packet::Broadcast); 322 dcache_pkt->allocate(); 323 dcache_pkt->set(data); |
324 |
325 if (!dcachePort.sendTiming(dcache_pkt)) { |
326 _status = DcacheRetry; |
327 } else { 328 _status = DcacheWaitResponse; |
329 // memory system takes ownership of packet |
330 dcache_pkt = NULL; 331 } 332 } 333 334 // This will need a new way to tell if it's hooked up to a cache or not. |
335 if (req->getFlags() & UNCACHEABLE) |
336 recordEvent("Uncached Write"); 337 338 // If the write needs to have a fault on the access, consider calling 339 // changeStatus() and changing it to "bad addr write" or something. 340 return fault; 341} 342 343 --- 336 unchanged lines hidden --- |