1/* 2 * Copyright (c) 2002-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 19 unchanged lines hidden (view full) --- 28 * Authors: Steve Reinhardt 29 */ 30 31#include "arch/utility.hh" 32#include "cpu/exetrace.hh" 33#include "cpu/simple/timing.hh" 34#include "mem/packet_impl.hh" 35#include "sim/builder.hh" |
36 37using namespace std; 38using namespace TheISA; 39 40Port * 41TimingSimpleCPU::getPort(const std::string &if_name, int idx) 42{ 43 if (if_name == "dcache_port") --- 42 unchanged lines hidden (view full) --- 86 87TimingSimpleCPU::TimingSimpleCPU(Params *p) 88 : BaseSimpleCPU(p), icachePort(this), dcachePort(this) 89{ 90 _status = Idle; 91 ifetch_pkt = dcache_pkt = NULL; 92 drainEvent = NULL; 93 fetchEvent = NULL; |
94 state = SimObject::Timing; |
95} 96 97 98TimingSimpleCPU::~TimingSimpleCPU() 99{ 100} 101 102void 103TimingSimpleCPU::serialize(ostream &os) 104{ |
105 SimObject::State so_state = SimObject::getState(); 106 SERIALIZE_ENUM(so_state); |
107 BaseSimpleCPU::serialize(os); 108} 109 110void 111TimingSimpleCPU::unserialize(Checkpoint *cp, const string §ion) 112{ |
113 SimObject::State so_state; 114 UNSERIALIZE_ENUM(so_state); |
115 BaseSimpleCPU::unserialize(cp, section); 116} 117 |
118bool |
119TimingSimpleCPU::drain(Event *drain_event) 120{ 121 // TimingSimpleCPU is ready to drain if it's not waiting for 122 // an access to complete. 123 if (status() == Idle || status() == Running || status() == SwitchedOut) { |
124 changeState(SimObject::DrainedTiming); 125 return true; |
126 } else { 127 changeState(SimObject::Draining); 128 drainEvent = drain_event; |
129 return false; |
130 } 131} 132 133void 134TimingSimpleCPU::resume() 135{ 136 if (_status != SwitchedOut && _status != Idle) { 137 // Delete the old event if it existed. 138 if (fetchEvent) { |
139 if (fetchEvent->scheduled()) 140 fetchEvent->deschedule(); 141 |
142 delete fetchEvent; 143 } 144 145 fetchEvent = 146 new EventWrapper<TimingSimpleCPU, &TimingSimpleCPU::fetch>(this, false); 147 fetchEvent->schedule(curTick); 148 } |
149} |
150 |
151void 152TimingSimpleCPU::setMemoryMode(State new_mode) 153{ 154 assert(new_mode == SimObject::Timing); |
155} 156 157void 158TimingSimpleCPU::switchOut() 159{ 160 assert(status() == Running || status() == Idle); 161 _status = SwitchedOut; 162 --- 350 unchanged lines hidden (view full) --- 513 advanceInst(fault); 514} 515 516 517void 518TimingSimpleCPU::completeDrain() 519{ 520 DPRINTF(Config, "Done draining\n"); |
521 changeState(SimObject::DrainedTiming); |
522 drainEvent->process(); 523} 524 525bool 526TimingSimpleCPU::DcachePort::recvTiming(Packet *pkt) 527{ 528 cpu->completeDataAccess(pkt); 529 return true; --- 20 unchanged lines hidden (view full) --- 550// 551BEGIN_DECLARE_SIM_OBJECT_PARAMS(TimingSimpleCPU) 552 553 Param<Counter> max_insts_any_thread; 554 Param<Counter> max_insts_all_threads; 555 Param<Counter> max_loads_any_thread; 556 Param<Counter> max_loads_all_threads; 557 SimObjectParam<MemObject *> mem; |
558 559#if FULL_SYSTEM 560 SimObjectParam<AlphaITB *> itb; 561 SimObjectParam<AlphaDTB *> dtb; |
562 SimObjectParam<System *> system; |
563 Param<int> cpu_id; 564 Param<Tick> profile; 565#else 566 SimObjectParam<Process *> workload; 567#endif // FULL_SYSTEM 568 569 Param<int> clock; 570 --- 11 unchanged lines hidden (view full) --- 582 "terminate when any thread reaches this inst count"), 583 INIT_PARAM(max_insts_all_threads, 584 "terminate when all threads have reached this inst count"), 585 INIT_PARAM(max_loads_any_thread, 586 "terminate when any thread reaches this load count"), 587 INIT_PARAM(max_loads_all_threads, 588 "terminate when all threads have reached this load count"), 589 INIT_PARAM(mem, "memory"), |
590 591#if FULL_SYSTEM 592 INIT_PARAM(itb, "Instruction TLB"), 593 INIT_PARAM(dtb, "Data TLB"), |
594 INIT_PARAM(system, "system object"), |
595 INIT_PARAM(cpu_id, "processor ID"), 596 INIT_PARAM(profile, ""), 597#else 598 INIT_PARAM(workload, "processes to run"), 599#endif // FULL_SYSTEM 600 601 INIT_PARAM(clock, "clock speed"), 602 INIT_PARAM(defer_registration, "defer system registration (for sampling)"), --- 14 unchanged lines hidden (view full) --- 617 params->max_insts_all_threads = max_insts_all_threads; 618 params->max_loads_any_thread = max_loads_any_thread; 619 params->max_loads_all_threads = max_loads_all_threads; 620 params->deferRegistration = defer_registration; 621 params->clock = clock; 622 params->functionTrace = function_trace; 623 params->functionTraceStart = function_trace_start; 624 params->mem = mem; |
625 626#if FULL_SYSTEM 627 params->itb = itb; 628 params->dtb = dtb; |
629 params->system = system; |
630 params->cpu_id = cpu_id; 631 params->profile = profile; 632#else 633 params->process = workload; 634#endif 635 636 TimingSimpleCPU *cpu = new TimingSimpleCPU(params); 637 return cpu; 638} 639 640REGISTER_SIM_OBJECT("TimingSimpleCPU", TimingSimpleCPU) 641 |