1/* 2 * Copyright (c) 2002-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 23 unchanged lines hidden (view full) --- 32#include "cpu/exetrace.hh" 33#include "cpu/simple/timing.hh" 34#include "mem/packet_impl.hh" 35#include "sim/builder.hh" 36 37using namespace std; 38using namespace TheISA; 39 |
40 41void 42TimingSimpleCPU::init() 43{ |
44 //Create Memory Ports (conect them up) 45 Port *mem_dport = mem->getPort(""); 46 dcachePort.setPeer(mem_dport); 47 mem_dport->setPeer(&dcachePort); 48 49 Port *mem_iport = mem->getPort(""); 50 icachePort.setPeer(mem_iport); 51 mem_iport->setPeer(&icachePort); 52 |
53 BaseCPU::init(); 54#if FULL_SYSTEM 55 for (int i = 0; i < threadContexts.size(); ++i) { 56 ThreadContext *tc = threadContexts[i]; 57 58 // initialize CPU, including PC 59 TheISA::initCPU(tc, tc->readCpuId()); 60 } --- 52 unchanged lines hidden (view full) --- 113 114bool 115TimingSimpleCPU::drain(Event *drain_event) 116{ 117 // TimingSimpleCPU is ready to drain if it's not waiting for 118 // an access to complete. 119 if (status() == Idle || status() == Running || status() == SwitchedOut) { 120 changeState(SimObject::DrainedTiming); |
121 return true; |
122 } else { 123 changeState(SimObject::Draining); 124 drainEvent = drain_event; |
125 return false; |
126 } 127} 128 129void 130TimingSimpleCPU::resume() 131{ 132 if (_status != SwitchedOut && _status != Idle) { 133 Event *e = --- 491 unchanged lines hidden --- |