1/* 2 * Copyright (c) 2002-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 144 unchanged lines hidden (view full) --- 153 154 155void 156TimingSimpleCPU::suspendContext(int thread_num) 157{ 158 assert(thread_num == 0); 159 assert(cpuXC); 160 |
161 assert(_status == Running); 162 |
163 // just change status to Idle... if status != Running, 164 // completeInst() will not initiate fetch of next instruction. 165 |
166 notIdleFraction--; 167 _status = Idle; 168} 169 170 171template <class T> 172Fault 173TimingSimpleCPU::read(Addr addr, T &data, unsigned flags) --- 179 unchanged lines hidden (view full) --- 353 _status = IcacheRetry; 354 } else { 355 // Need to wait for cache to respond 356 _status = IcacheWaitResponse; 357 // ownership of packet transferred to memory system 358 ifetch_pkt = NULL; 359 } 360 } else { |
361 // fetch fault: advance directly to next instruction (fault handler) 362 advanceInst(fault); |
363 } 364} 365 366 367void |
368TimingSimpleCPU::advanceInst(Fault fault) |
369{ |
370 advancePC(fault); 371 372 if (_status == Running) { 373 // kick off fetch of next instruction... callback from icache 374 // response will cause that instruction to be executed, 375 // keeping the CPU running. 376 fetch(); 377 } 378} 379 380 381void |
382TimingSimpleCPU::completeIfetch(Packet *pkt) |
383{ 384 // received a response from the icache: execute the received 385 // instruction |
386 assert(pkt->result == Packet::Success); |
387 assert(_status == IcacheWaitResponse); 388 _status = Running; |
389 390 delete pkt->req; 391 delete pkt; 392 |
393 preExecute(); |
394 if (curStaticInst->isMemRef() && !curStaticInst->isDataPrefetch()) { |
395 // load or store: just send to dcache 396 Fault fault = curStaticInst->initiateAcc(this, traceData); |
397 if (fault == NoFault) { 398 // successfully initiated access: instruction will 399 // complete in dcache response callback 400 assert(_status == DcacheWaitResponse); 401 } else { 402 // fault: complete now to invoke fault handler 403 postExecute(); 404 advanceInst(fault); 405 } |
406 } else { 407 // non-memory instruction: execute completely now 408 Fault fault = curStaticInst->execute(this, traceData); |
409 postExecute(); 410 advanceInst(fault); |
411 } 412} 413 414 415bool 416TimingSimpleCPU::IcachePort::recvTiming(Packet *pkt) 417{ |
418 cpu->completeIfetch(pkt); |
419 return true; 420} 421 422Packet * 423TimingSimpleCPU::IcachePort::recvRetry() 424{ 425 // we shouldn't get a retry unless we have a packet that we're 426 // waiting to transmit --- 11 unchanged lines hidden (view full) --- 438 // received a response from the dcache: complete the load or store 439 // instruction 440 assert(pkt->result == Packet::Success); 441 assert(_status == DcacheWaitResponse); 442 _status = Running; 443 444 Fault fault = curStaticInst->completeAcc(pkt, this, traceData); 445 |
446 delete pkt->req; 447 delete pkt; 448 449 postExecute(); 450 advanceInst(fault); |
451} 452 453 454 455bool 456TimingSimpleCPU::DcachePort::recvTiming(Packet *pkt) 457{ 458 cpu->completeDataAccess(pkt); --- 112 unchanged lines hidden --- |