| 1/* 2 * Copyright 2014 Google, Inc. |
| 3 * Copyright (c) 2010-2013,2015,2017-2018 ARM Limited |
| 4 * All rights reserved 5 * 6 * The license below extends only to copyright in the software and shall 7 * not be construed as granting a license to any other intellectual 8 * property including but not limited to intellectual property relating 9 * to a hardware implementation of the functionality of the software 10 * licensed hereunder. You may use the software subject to the license 11 * terms below provided that you ensure that this notice is replicated --- 400 unchanged lines hidden (view full) --- 412 main_send_state->fragments[1] = pkt2; 413 main_send_state->outstanding = 2; 414 pkt1->senderState = new SplitFragmentSenderState(pkt, 0); 415 pkt2->senderState = new SplitFragmentSenderState(pkt, 1); 416} 417 418Fault 419TimingSimpleCPU::initiateMemRead(Addr addr, unsigned size, |
| 420 Request::Flags flags, 421 const std::vector<bool>& byteEnable) |
| 422{ 423 SimpleExecContext &t_info = *threadInfo[curThread]; 424 SimpleThread* thread = t_info.thread; 425 426 Fault fault; 427 const int asid = 0; 428 const Addr pc = thread->instAddr(); 429 unsigned block_size = cacheLineSize(); 430 BaseTLB::Mode mode = BaseTLB::Read; 431 432 if (traceData) 433 traceData->setMem(addr, size, flags); 434 435 RequestPtr req = std::make_shared<Request>( 436 asid, addr, size, flags, dataMasterId(), pc, 437 thread->contextId()); |
| 438 if (!byteEnable.empty()) { 439 req->setByteEnable(byteEnable); 440 } |
| 441 442 req->taskId(taskId()); 443 444 Addr split_addr = roundDown(addr + size - 1, block_size); 445 assert(split_addr <= addr || split_addr - addr < block_size); 446 447 _status = DTBWaitResponse; 448 if (split_addr > addr) { --- 41 unchanged lines hidden (view full) --- 490 // memory system takes ownership of packet 491 dcache_pkt = NULL; 492 } 493 return dcache_pkt == NULL; 494} 495 496Fault 497TimingSimpleCPU::writeMem(uint8_t *data, unsigned size, |
| 498 Addr addr, Request::Flags flags, uint64_t *res, 499 const std::vector<bool>& byteEnable) |
| 500{ 501 SimpleExecContext &t_info = *threadInfo[curThread]; 502 SimpleThread* thread = t_info.thread; 503 504 uint8_t *newData = new uint8_t[size]; 505 const int asid = 0; 506 const Addr pc = thread->instAddr(); 507 unsigned block_size = cacheLineSize(); --- 8 unchanged lines hidden (view full) --- 516 } 517 518 if (traceData) 519 traceData->setMem(addr, size, flags); 520 521 RequestPtr req = std::make_shared<Request>( 522 asid, addr, size, flags, dataMasterId(), pc, 523 thread->contextId()); |
| 524 if (!byteEnable.empty()) { 525 req->setByteEnable(byteEnable); 526 } |
| 527 528 req->taskId(taskId()); 529 530 Addr split_addr = roundDown(addr + size - 1, block_size); 531 assert(split_addr <= addr || split_addr - addr < block_size); 532 533 _status = DTBWaitResponse; |
| 534 535 // TODO: TimingSimpleCPU doesn't support arbitrarily long multi-line mem. 536 // accesses yet 537 |
| 538 if (split_addr > addr) { 539 RequestPtr req1, req2; 540 assert(!req->isLLSC() && !req->isSwap()); 541 req->splitOnVaddr(split_addr, req1, req2); 542 543 WholeTranslationState *state = 544 new WholeTranslationState(req, req1, req2, newData, res, mode); 545 DataTranslation<TimingSimpleCPU *> *trans1 = --- 536 unchanged lines hidden --- |