56a57
> #include "sim/full_system.hh"
76a78,79
> if (FullSystem) {
> for (int i = 0; i < threadContexts.size(); ++i) {
78,79c81,87
< for (int i = 0; i < threadContexts.size(); ++i) {
< ThreadContext *tc = threadContexts[i];
---
> ThreadContext *tc = threadContexts[i];
> // initialize CPU, including PC
> TheISA::initCPU(tc, _cpuId);
> #endif
> }
> }
> }
81,82c89,111
< // initialize CPU, including PC
< TheISA::initCPU(tc, _cpuId);
---
> Tick
> TimingSimpleCPU::CpuPort::recvAtomic(PacketPtr pkt)
> {
> panic("TimingSimpleCPU doesn't expect recvAtomic callback!");
> return curTick();
> }
>
> void
> TimingSimpleCPU::CpuPort::recvFunctional(PacketPtr pkt)
> {
> //No internal storage to update, jusst return
> return;
> }
>
> void
> TimingSimpleCPU::CpuPort::recvStatusChange(Status status)
> {
> if (status == RangeChange) {
> if (!snoopRangeSent) {
> snoopRangeSent = true;
> sendStatusChange(Port::RangeChange);
> }
> return;
85,87c114
< // Initialise the ThreadContext's memory proxies
< tcBase()->initMemProxies(tcBase());
< #endif
---
> panic("TimingSimpleCPU doesn't expect recvStatusChange callback!");
89a117
>
91c119
< TimingSimpleCPU::TimingCPUPort::TickEvent::schedule(PacketPtr _pkt, Tick t)
---
> TimingSimpleCPU::CpuPort::TickEvent::schedule(PacketPtr _pkt, Tick t)
98,99c126,127
< : BaseSimpleCPU(p), fetchTranslation(this), icachePort(this),
< dcachePort(this), fetchEvent(this)
---
> : BaseSimpleCPU(p), fetchTranslation(this), icachePort(this, p->clock),
> dcachePort(this, p->clock), fetchEvent(this)
102a131,133
> icachePort.snoopRangeSent = false;
> dcachePort.snoopRangeSent = false;
>
179c210
< BaseCPU::takeOverFrom(oldCPU);
---
> BaseCPU::takeOverFrom(oldCPU, &icachePort, &dcachePort);
200c231
< TimingSimpleCPU::activateContext(ThreadID thread_num, int delay)
---
> TimingSimpleCPU::activateContext(int thread_num, int delay)
218c249
< TimingSimpleCPU::suspendContext(ThreadID thread_num)
---
> TimingSimpleCPU::suspendContext(int thread_num)
847a879,890
> void
> TimingSimpleCPU::DcachePort::setPeer(Port *port)
> {
> Port::setPeer(port);
>
> if (FullSystem) {
> // Update the ThreadContext's memory ports (Functional/Virtual
> // Ports)
> cpu->tcBase()->connectMemPorts(cpu->tcBase());
> }
> }
>
865c908
< cpu->schedule(retryEvent, next_tick);
---
> schedule(retryEvent, next_tick);
970c1013
< if (workload.size() != 1)
---
> if (!FullSystem && workload.size() != 1)