277a278
> delete req1;
288a290,298
> if (req->getFlags().isSet(Request::NO_ACCESS)) {
> delete req1;
> delete pkt1;
> delete req2;
> delete pkt2;
> pkt1 = pkt;
> pkt2 = NULL;
> return NoFault;
> }
307,308c317
< Fault fault = read ? thread->translateDataReadReq(req) :
< thread->translateDataWriteReq(req);
---
> Fault fault = thread->dtb->translate(req, tc, !read);
351c360
< this->buildSplitPacket(pkt1, pkt2, req,
---
> Fault fault = this->buildSplitPacket(pkt1, pkt2, req,
353c362,366
< if (handleReadPacket(pkt1)) {
---
> if (fault != NoFault)
> return fault;
> if (req->getFlags().isSet(Request::NO_ACCESS)) {
> dcache_pkt = pkt1;
> } else if (handleReadPacket(pkt1)) {
368,370c381,386
< pkt->dataDynamic<T>(new T);
<
< handleReadPacket(pkt);
---
> if (req->getFlags().isSet(Request::NO_ACCESS)) {
> dcache_pkt = pkt;
> } else {
> pkt->dataDynamic<T>(new T);
> handleReadPacket(pkt);
> }
385,404d400
< Fault
< TimingSimpleCPU::translateDataReadAddr(Addr vaddr, Addr &paddr,
< int size, unsigned flags)
< {
< Request *req =
< new Request(0, vaddr, size, flags, thread->readPC(), _cpuId, 0);
<
< if (traceData) {
< traceData->setAddr(vaddr);
< }
<
< Fault fault = thread->translateDataWriteReq(req);
<
< if (fault == NoFault)
< paddr = req->getPaddr();
<
< delete req;
< return fault;
< }
<
500,507c496,500
< if (handleWritePacket()) {
< SplitFragmentSenderState * send_state =
< dynamic_cast<SplitFragmentSenderState *>(pkt1->senderState);
< send_state->clearFromParent();
< dcache_pkt = pkt2;
< if (handleReadPacket(pkt2)) {
< send_state =
< dynamic_cast<SplitFragmentSenderState *>(pkt1->senderState);
---
> if (!req->getFlags().isSet(Request::NO_ACCESS)) {
> if (handleWritePacket()) {
> SplitFragmentSenderState * send_state =
> dynamic_cast<SplitFragmentSenderState *>(
> pkt1->senderState);
508a502,508
> dcache_pkt = pkt2;
> if (handleReadPacket(pkt2)) {
> send_state =
> dynamic_cast<SplitFragmentSenderState *>(
> pkt1->senderState);
> send_state->clearFromParent();
> }
518,523c518,524
< if (req->isLocked()) {
< do_access = TheISA::handleLockedWrite(thread, req);
< } else if (req->isCondSwap()) {
< assert(res);
< req->setExtraData(*res);
< }
---
> if (!req->getFlags().isSet(Request::NO_ACCESS)) {
> if (req->isLocked()) {
> do_access = TheISA::handleLockedWrite(thread, req);
> } else if (req->isCondSwap()) {
> assert(res);
> req->setExtraData(*res);
> }
525,529c526,530
< dcache_pkt->allocate();
< if (req->isMmapedIpr())
< dcache_pkt->set(htog(data));
< else
< dcache_pkt->set(data);
---
> dcache_pkt->allocate();
> if (req->isMmapedIpr())
> dcache_pkt->set(htog(data));
> else
> dcache_pkt->set(data);
531,532c532,534
< if (do_access)
< handleWritePacket();
---
> if (do_access)
> handleWritePacket();
> }
549,554d550
< Fault
< TimingSimpleCPU::translateDataWriteAddr(Addr vaddr, Addr &paddr,
< int size, unsigned flags)
< {
< Request *req =
< new Request(0, vaddr, size, flags, thread->readPC(), _cpuId, 0);
556,569d551
< if (traceData) {
< traceData->setAddr(vaddr);
< }
<
< Fault fault = thread->translateDataWriteReq(req);
<
< if (fault == NoFault)
< paddr = req->getPaddr();
<
< delete req;
< return fault;
< }
<
<