31a32
> #include "arch/mmaped_ipr.hh"
269c270,276
< if (!dcachePort.sendTiming(pkt)) {
---
> if (req->isMmapedIpr()) {
> Tick delay;
> delay = TheISA::handleIprRead(thread->getTC(), pkt);
> new IprEvent(pkt, this, nextCycle(curTick + delay));
> _status = DcacheWaitResponse;
> dcache_pkt = NULL;
> } else if (!dcachePort.sendTiming(pkt)) {
378c385,392
< if (!dcachePort.sendTiming(dcache_pkt)) {
---
> if (req->isMmapedIpr()) {
> Tick delay;
> dcache_pkt->set(htog(data));
> delay = TheISA::handleIprWrite(thread->getTC(), dcache_pkt);
> new IprEvent(dcache_pkt, this, nextCycle(curTick + delay));
> _status = DcacheWaitResponse;
> dcache_pkt = NULL;
> } else if (!dcachePort.sendTiming(dcache_pkt)) {
553a568,571
> // @todo remove me after debugging with legion done
> if (curStaticInst && (!curStaticInst->isMicroop() ||
> curStaticInst->isFirstMicroop()))
> instCnt++;
569a588,591
> // @todo remove me after debugging with legion done
> if (curStaticInst && (!curStaticInst->isMicroop() ||
> curStaticInst->isFirstMicroop()))
> instCnt++;
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> TimingSimpleCPU::IprEvent::IprEvent(Packet *_pkt, TimingSimpleCPU *_cpu, Tick t)
> : Event(&mainEventQueue), pkt(_pkt), cpu(_cpu)
> {
> schedule(t);
> }
733a761,773
> void
> TimingSimpleCPU::IprEvent::process()
> {
> cpu->completeDataAccess(pkt);
> }
>
> const char *
> TimingSimpleCPU::IprEvent::description()
> {
> return "Timing Simple CPU Delay IPR event";
> }
>
>