30a31
> #include "arch/locked_mem.hh"
97c98,99
< : BaseSimpleCPU(p), icachePort(this, p->clock), dcachePort(this, p->clock)
---
> : BaseSimpleCPU(p), icachePort(this, p->clock), dcachePort(this, p->clock),
> cpu_id(p->cpu_id)
232c234
< /* CPU ID */ 0, /* thread ID */ 0);
---
> cpu_id, /* thread ID */ 0);
313c315
< /* CPU ID */ 0, /* thread ID */ 0);
---
> cpu_id, /* thread ID */ 0);
325,330c327,330
< if (!dcachePort.sendTiming(dcache_pkt)) {
< _status = DcacheRetry;
< } else {
< _status = DcacheWaitResponse;
< // memory system takes ownership of packet
< dcache_pkt = NULL;
---
> bool do_access = true; // flag to suppress cache access
>
> if (req->isLocked()) {
> do_access = TheISA::handleLockedWrite(thread, req);
331a332,341
>
> if (do_access) {
> if (!dcachePort.sendTiming(dcache_pkt)) {
> _status = DcacheRetry;
> } else {
> _status = DcacheWaitResponse;
> // memory system takes ownership of packet
> dcache_pkt = NULL;
> }
> }
395d404
< // need to fill in CPU & thread IDs here
397c406
< ifetch_req->setThreadContext(0,0); //Need CPU/Thread IDS HERE
---
> ifetch_req->setThreadContext(cpu_id, /* thread ID */ 0);
456,459c465,468
< if (fault == NoFault) {
< // successfully initiated access: instruction will
< // complete in dcache response callback
< assert(_status == DcacheWaitResponse);
---
> if (_status != Running) {
> // instruction will complete in dcache response callback
> assert(_status == DcacheWaitResponse || _status == DcacheRetry);
> assert(fault == NoFault);
461c470,478
< // fault: complete now to invoke fault handler
---
> if (fault == NoFault) {
> // early fail on store conditional: complete now
> assert(dcache_pkt != NULL);
> fault = curStaticInst->completeAcc(dcache_pkt, this,
> traceData);
> delete dcache_pkt->req;
> delete dcache_pkt;
> dcache_pkt = NULL;
> }
482,483c499
< // These next few lines could be replaced with something faster
< // who knows what though
---
> // delay processing of returned data until next CPU clock edge
529a546,549
> if (pkt->isRead() && pkt->req->isLocked()) {
> TheISA::handleLockedRead(thread, pkt->req);
> }
>
548a569
> // delay processing of returned data until next CPU clock edge
576a598
> // memory system takes ownership of packet
594a617
> Param<int> cpu_id;
599d621
< Param<int> cpu_id;
627a650
> INIT_PARAM(cpu_id, "processor ID"),
632d654
< INIT_PARAM(cpu_id, "processor ID"),
663a686
> params->cpu_id = cpu_id;
668d690
< params->cpu_id = cpu_id;