230,233c230,232
< // need to fill in CPU & thread IDs here
< Request *data_read_req = new Request();
< data_read_req->setThreadContext(0,0); //Need CPU/Thread IDS HERE
< data_read_req->setVirt(0, addr, sizeof(T), flags, thread->readPC());
---
> Request *req =
> new Request(/* asid */ 0, addr, sizeof(T), flags, thread->readPC(),
> /* CPU ID */ 0, /* thread ID */ 0);
236c235
< traceData->setAddr(data_read_req->getVaddr());
---
> traceData->setAddr(req->getVaddr());
240c239
< Fault fault = thread->translateDataReadReq(data_read_req);
---
> Fault fault = thread->translateDataReadReq(req);
244,246c243,245
< Packet *data_read_pkt =
< new Packet(data_read_req, Packet::ReadReq, Packet::Broadcast);
< data_read_pkt->dataDynamic<T>(new T);
---
> Packet *pkt =
> new Packet(req, Packet::ReadReq, Packet::Broadcast);
> pkt->dataDynamic<T>(new T);
248c247
< if (!dcachePort.sendTiming(data_read_pkt)) {
---
> if (!dcachePort.sendTiming(pkt)) {
250c249
< dcache_pkt = data_read_pkt;
---
> dcache_pkt = pkt;
252a252
> // memory system takes ownership of packet
258c258
< if (data_read_req->getFlags() & UNCACHEABLE)
---
> if (req->getFlags() & UNCACHEABLE)
311,314c311,313
< // need to fill in CPU & thread IDs here
< Request *data_write_req = new Request();
< data_write_req->setThreadContext(0,0); //Need CPU/Thread IDS HERE
< data_write_req->setVirt(0, addr, sizeof(T), flags, thread->readPC());
---
> Request *req =
> new Request(/* asid */ 0, addr, sizeof(T), flags, thread->readPC(),
> /* CPU ID */ 0, /* thread ID */ 0);
317c316,317
< Fault fault = thread->translateDataWriteReq(data_write_req);
---
> Fault fault = thread->translateDataWriteReq(req);
>
320,323c320,323
< Packet *data_write_pkt =
< new Packet(data_write_req, Packet::WriteReq, Packet::Broadcast);
< data_write_pkt->allocate();
< data_write_pkt->set(data);
---
> assert(dcache_pkt == NULL);
> dcache_pkt = new Packet(req, Packet::WriteReq, Packet::Broadcast);
> dcache_pkt->allocate();
> dcache_pkt->set(data);
325c325
< if (!dcachePort.sendTiming(data_write_pkt)) {
---
> if (!dcachePort.sendTiming(dcache_pkt)) {
327d326
< dcache_pkt = data_write_pkt;
329a329
> // memory system takes ownership of packet
335c335
< if (data_write_req->getFlags() & UNCACHEABLE)
---
> if (req->getFlags() & UNCACHEABLE)