40,49d39
< Port *
< TimingSimpleCPU::getPort(const std::string &if_name, int idx)
< {
< if (if_name == "dcache_port")
< return &dcachePort;
< else if (if_name == "icache_port")
< return &icachePort;
< else
< panic("No Such Port\n");
< }
53a44,52
> //Create Memory Ports (conect them up)
> Port *mem_dport = mem->getPort("");
> dcachePort.setPeer(mem_dport);
> mem_dport->setPeer(&dcachePort);
>
> Port *mem_iport = mem->getPort("");
> icachePort.setPeer(mem_iport);
> mem_iport->setPeer(&icachePort);
>
122c121
< return false;
---
> return true;
126c125
< return true;
---
> return false;