90a91,92
> quiesceEvent = NULL;
> state = SimObject::Timing;
101d102
< BaseSimpleCPU::serialize(os);
102a104
> BaseSimpleCPU::serialize(os);
108d109
< BaseSimpleCPU::unserialize(cp, section);
109a111
> BaseSimpleCPU::unserialize(cp, section);
111a114,129
> bool
> TimingSimpleCPU::quiesce(Event *quiesce_event)
> {
> // TimingSimpleCPU is ready to quiesce if it's not waiting for
> // an access to complete.
> if (status() == Idle || status() == Running || status() == SwitchedOut) {
> DPRINTF(Config, "Ready to quiesce\n");
> return false;
> } else {
> DPRINTF(Config, "Waiting to quiesce\n");
> changeState(SimObject::Quiescing);
> quiesceEvent = quiesce_event;
> return true;
> }
> }
>
113c131
< TimingSimpleCPU::switchOut(Sampler *s)
---
> TimingSimpleCPU::resume()
115,117c133,136
< sampler = s;
< if (status() == Running) {
< _status = SwitchedOut;
---
> if (_status != SwitchedOut && _status != Idle) {
> Event *e =
> new EventWrapper<TimingSimpleCPU, &TimingSimpleCPU::fetch>(this, true);
> e->schedule(curTick);
119d137
< sampler->signalSwitched();
121a140,144
> void
> TimingSimpleCPU::setMemoryMode(State new_mode)
> {
> assert(new_mode == SimObject::Timing);
> }
123a147,154
> TimingSimpleCPU::switchOut()
> {
> assert(status() == Running || status() == Idle);
> _status = SwitchedOut;
> }
>
>
> void
385a417
>
390a423,427
> if (getState() == SimObject::Quiescing) {
> completeQuiesce();
> return;
> }
>
442a480,488
> if (getState() == SimObject::Quiescing) {
> completeQuiesce();
>
> delete pkt->req;
> delete pkt;
>
> return;
> }
>
452a499,505
> void
> TimingSimpleCPU::completeQuiesce()
> {
> DPRINTF(Config, "Done quiescing\n");
> changeState(SimObject::QuiescedTiming);
> quiesceEvent->process();
> }