161,162d160
< panic("TimingSimpleCPU::suspendContext not implemented");
<
164a163,165
> // just change status to Idle... if status != Running,
> // completeInst() will not initiate fetch of next instruction.
>
360c361,362
< panic("TimingSimpleCPU fetch fault handling not implemented");
---
> // fetch fault: advance directly to next instruction (fault handler)
> advanceInst(fault);
366c368
< TimingSimpleCPU::completeInst(Fault fault)
---
> TimingSimpleCPU::advanceInst(Fault fault)
368,373d369
< postExecute();
<
< if (traceData) {
< traceData->finalize();
< }
<
386c382
< TimingSimpleCPU::completeIfetch()
---
> TimingSimpleCPU::completeIfetch(Packet *pkt)
389a386
> assert(pkt->result == Packet::Success);
391a389,392
>
> delete pkt->req;
> delete pkt;
>
393c394
< if (curStaticInst->isMemRef()) {
---
> if (curStaticInst->isMemRef() && !curStaticInst->isDataPrefetch()) {
396,398c397,405
< assert(fault == NoFault);
< assert(_status == DcacheWaitResponse);
< // instruction will complete in dcache response callback
---
> if (fault == NoFault) {
> // successfully initiated access: instruction will
> // complete in dcache response callback
> assert(_status == DcacheWaitResponse);
> } else {
> // fault: complete now to invoke fault handler
> postExecute();
> advanceInst(fault);
> }
402c409,410
< completeInst(fault);
---
> postExecute();
> advanceInst(fault);
410c418
< cpu->completeIfetch();
---
> cpu->completeIfetch(pkt);
438c446,450
< completeInst(fault);
---
> delete pkt->req;
> delete pkt;
>
> postExecute();
> advanceInst(fault);