3c3
< * Copyright (c) 2010-2013,2015,2017 ARM Limited
---
> * Copyright (c) 2010-2013,2015,2017-2018 ARM Limited
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< Request::Flags flags)
---
> Request::Flags flags,
> const std::vector<bool>& byteEnable)
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> if (!byteEnable.empty()) {
> req->setByteEnable(byteEnable);
> }
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< Addr addr, Request::Flags flags, uint64_t *res)
---
> Addr addr, Request::Flags flags, uint64_t *res,
> const std::vector<bool>& byteEnable)
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> if (!byteEnable.empty()) {
> req->setByteEnable(byteEnable);
> }
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>
> // TODO: TimingSimpleCPU doesn't support arbitrarily long multi-line mem.
> // accesses yet
>