1/*
2 * Copyright (c) 2010-2012 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2002-2005 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Steve Reinhardt
41 */
42
43#include "arch/locked_mem.hh"
44#include "arch/mmapped_ipr.hh"
45#include "arch/utility.hh"
46#include "base/bigint.hh"
47#include "config/the_isa.hh"
48#include "cpu/simple/timing.hh"
49#include "cpu/exetrace.hh"
50#include "debug/Config.hh"
51#include "debug/Drain.hh"
52#include "debug/ExecFaulting.hh"
53#include "debug/SimpleCPU.hh"
54#include "mem/packet.hh"
55#include "mem/packet_access.hh"
56#include "params/TimingSimpleCPU.hh"
57#include "sim/faults.hh"
58#include "sim/full_system.hh"
59#include "sim/system.hh"
60
61using namespace std;
62using namespace TheISA;
63
64void
65TimingSimpleCPU::init()
66{
67 BaseCPU::init();
68
69 if (!params()->switched_out &&
70 system->getMemoryMode() != Enums::timing) {
71 fatal("The timing CPU requires the memory system to be in "
72 "'timing' mode.\n");
73 }
74
75 // Initialise the ThreadContext's memory proxies
76 tcBase()->initMemProxies(tcBase());
77
78 if (FullSystem && !params()->switched_out) {
79 for (int i = 0; i < threadContexts.size(); ++i) {
80 ThreadContext *tc = threadContexts[i];
81 // initialize CPU, including PC
82 TheISA::initCPU(tc, _cpuId);
83 }
84 }
85}
86
87void
88TimingSimpleCPU::TimingCPUPort::TickEvent::schedule(PacketPtr _pkt, Tick t)
89{
90 pkt = _pkt;
91 cpu->schedule(this, t);
92}
93
94TimingSimpleCPU::TimingSimpleCPU(TimingSimpleCPUParams *p)
95 : BaseSimpleCPU(p), fetchTranslation(this), icachePort(this),
96 dcachePort(this), ifetch_pkt(NULL), dcache_pkt(NULL), previousCycle(0),
| 1/*
2 * Copyright (c) 2010-2012 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software
9 * licensed hereunder. You may use the software subject to the license
10 * terms below provided that you ensure that this notice is replicated
11 * unmodified and in its entirety in all distributions of the software,
12 * modified or unmodified, in source code or in binary form.
13 *
14 * Copyright (c) 2002-2005 The Regents of The University of Michigan
15 * All rights reserved.
16 *
17 * Redistribution and use in source and binary forms, with or without
18 * modification, are permitted provided that the following conditions are
19 * met: redistributions of source code must retain the above copyright
20 * notice, this list of conditions and the following disclaimer;
21 * redistributions in binary form must reproduce the above copyright
22 * notice, this list of conditions and the following disclaimer in the
23 * documentation and/or other materials provided with the distribution;
24 * neither the name of the copyright holders nor the names of its
25 * contributors may be used to endorse or promote products derived from
26 * this software without specific prior written permission.
27 *
28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
29 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
30 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
31 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
32 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
33 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
34 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
35 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
36 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
37 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
38 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
39 *
40 * Authors: Steve Reinhardt
41 */
42
43#include "arch/locked_mem.hh"
44#include "arch/mmapped_ipr.hh"
45#include "arch/utility.hh"
46#include "base/bigint.hh"
47#include "config/the_isa.hh"
48#include "cpu/simple/timing.hh"
49#include "cpu/exetrace.hh"
50#include "debug/Config.hh"
51#include "debug/Drain.hh"
52#include "debug/ExecFaulting.hh"
53#include "debug/SimpleCPU.hh"
54#include "mem/packet.hh"
55#include "mem/packet_access.hh"
56#include "params/TimingSimpleCPU.hh"
57#include "sim/faults.hh"
58#include "sim/full_system.hh"
59#include "sim/system.hh"
60
61using namespace std;
62using namespace TheISA;
63
64void
65TimingSimpleCPU::init()
66{
67 BaseCPU::init();
68
69 if (!params()->switched_out &&
70 system->getMemoryMode() != Enums::timing) {
71 fatal("The timing CPU requires the memory system to be in "
72 "'timing' mode.\n");
73 }
74
75 // Initialise the ThreadContext's memory proxies
76 tcBase()->initMemProxies(tcBase());
77
78 if (FullSystem && !params()->switched_out) {
79 for (int i = 0; i < threadContexts.size(); ++i) {
80 ThreadContext *tc = threadContexts[i];
81 // initialize CPU, including PC
82 TheISA::initCPU(tc, _cpuId);
83 }
84 }
85}
86
87void
88TimingSimpleCPU::TimingCPUPort::TickEvent::schedule(PacketPtr _pkt, Tick t)
89{
90 pkt = _pkt;
91 cpu->schedule(this, t);
92}
93
94TimingSimpleCPU::TimingSimpleCPU(TimingSimpleCPUParams *p)
95 : BaseSimpleCPU(p), fetchTranslation(this), icachePort(this),
96 dcachePort(this), ifetch_pkt(NULL), dcache_pkt(NULL), previousCycle(0),
|
97 fetchEvent(this)
| 97 fetchEvent(this), drainManager(NULL)
|
98{
99 _status = Idle;
100
| 98{
99 _status = Idle;
100
|
101 setDrainState(Drainable::Running);
| |
102 system->totalNumInsts = 0;
103}
104
105
106TimingSimpleCPU::~TimingSimpleCPU()
107{
108}
109
| 101 system->totalNumInsts = 0;
102}
103
104
105TimingSimpleCPU::~TimingSimpleCPU()
106{
107}
108
|
110void
111TimingSimpleCPU::serialize(ostream &os)
112{
113 Drainable::State so_state(getDrainState());
114 SERIALIZE_ENUM(so_state);
115 BaseSimpleCPU::serialize(os);
116}
117
118void
119TimingSimpleCPU::unserialize(Checkpoint *cp, const string §ion)
120{
121 Drainable::State so_state;
122 UNSERIALIZE_ENUM(so_state);
123 BaseSimpleCPU::unserialize(cp, section);
124}
125
| |
126unsigned int
127TimingSimpleCPU::drain(DrainManager *drain_manager)
128{
| 109unsigned int
110TimingSimpleCPU::drain(DrainManager *drain_manager)
111{
|
129 // TimingSimpleCPU is ready to drain if it's not waiting for
130 // an access to complete.
| |
131 if (_status == Idle ||
| 112 if (_status == Idle ||
|
132 _status == BaseSimpleCPU::Running ||
| 113 (_status == BaseSimpleCPU::Running && isDrained()) ||
|
133 _status == SwitchedOut) {
| 114 _status == SwitchedOut) {
|
134 setDrainState(Drainable::Drained);
| 115 assert(!fetchEvent.scheduled());
116 DPRINTF(Drain, "No need to drain.\n");
|
135 return 0;
136 } else {
| 117 return 0;
118 } else {
|
137 setDrainState(Drainable::Draining);
| |
138 drainManager = drain_manager;
| 119 drainManager = drain_manager;
|
139 DPRINTF(Drain, "CPU not drained\n");
| 120 DPRINTF(Drain, "Requesting drain: %s\n", pcState());
121
122 // The fetch event can become descheduled if a drain didn't
123 // succeed on the first attempt. We need to reschedule it if
124 // the CPU is waiting for a microcode routine to complete.
125 if (_status == BaseSimpleCPU::Running && !isDrained() &&
126 !fetchEvent.scheduled()) {
127 schedule(fetchEvent, nextCycle());
128 }
129
|
140 return 1;
141 }
142}
143
144void
145TimingSimpleCPU::drainResume()
146{
| 130 return 1;
131 }
132}
133
134void
135TimingSimpleCPU::drainResume()
136{
|
| 137 assert(!fetchEvent.scheduled());
138
|
147 DPRINTF(SimpleCPU, "Resume\n");
148 if (_status != SwitchedOut && _status != Idle) {
149 if (system->getMemoryMode() != Enums::timing) {
150 fatal("The timing CPU requires the memory system to be in "
151 "'timing' mode.\n");
152 }
153
| 139 DPRINTF(SimpleCPU, "Resume\n");
140 if (_status != SwitchedOut && _status != Idle) {
141 if (system->getMemoryMode() != Enums::timing) {
142 fatal("The timing CPU requires the memory system to be in "
143 "'timing' mode.\n");
144 }
145
|
154 if (fetchEvent.scheduled())
155 deschedule(fetchEvent);
156
| |
157 schedule(fetchEvent, nextCycle());
158 }
| 146 schedule(fetchEvent, nextCycle());
147 }
|
| 148}
|
159
| 149
|
160 setDrainState(Drainable::Running);
| 150bool
151TimingSimpleCPU::tryCompleteDrain()
152{
153 if (!drainManager)
154 return false;
155
156 DPRINTF(Drain, "tryCompleteDrain: %s\n", pcState());
157 if (!isDrained())
158 return false;
159
160 DPRINTF(Drain, "CPU done draining, processing drain event\n");
161 drainManager->signalDrainDone();
162 drainManager = NULL;
163
164 return true;
|
161}
162
163void
164TimingSimpleCPU::switchOut()
165{
166 BaseSimpleCPU::switchOut();
167
| 165}
166
167void
168TimingSimpleCPU::switchOut()
169{
170 BaseSimpleCPU::switchOut();
171
|
| 172 assert(!fetchEvent.scheduled());
|
168 assert(_status == BaseSimpleCPU::Running || _status == Idle);
| 173 assert(_status == BaseSimpleCPU::Running || _status == Idle);
|
| 174 assert(!stayAtPC);
175 assert(microPC() == 0);
176
|
169 _status = SwitchedOut;
170 numCycles += curCycle() - previousCycle;
| 177 _status = SwitchedOut;
178 numCycles += curCycle() - previousCycle;
|
171
172 // If we've been scheduled to resume but are then told to switch out,
173 // we'll need to cancel it.
174 if (fetchEvent.scheduled())
175 deschedule(fetchEvent);
| |
176}
177
178
179void
180TimingSimpleCPU::takeOverFrom(BaseCPU *oldCPU)
181{
182 BaseSimpleCPU::takeOverFrom(oldCPU);
183
184 // if any of this CPU's ThreadContexts are active, mark the CPU as
185 // running and schedule its tick event.
186 for (int i = 0; i < threadContexts.size(); ++i) {
187 ThreadContext *tc = threadContexts[i];
188 if (tc->status() == ThreadContext::Active &&
189 _status != BaseSimpleCPU::Running) {
190 _status = BaseSimpleCPU::Running;
191 break;
192 }
193 }
194
195 if (_status != BaseSimpleCPU::Running) {
196 _status = Idle;
197 }
198 assert(threadContexts.size() == 1);
199 previousCycle = curCycle();
200}
201
202
203void
204TimingSimpleCPU::activateContext(ThreadID thread_num, Cycles delay)
205{
206 DPRINTF(SimpleCPU, "ActivateContext %d (%d cycles)\n", thread_num, delay);
207
208 assert(thread_num == 0);
209 assert(thread);
210
211 assert(_status == Idle);
212
213 notIdleFraction++;
214 _status = BaseSimpleCPU::Running;
215
216 // kick things off by initiating the fetch of the next instruction
217 schedule(fetchEvent, clockEdge(delay));
218}
219
220
221void
222TimingSimpleCPU::suspendContext(ThreadID thread_num)
223{
224 DPRINTF(SimpleCPU, "SuspendContext %d\n", thread_num);
225
226 assert(thread_num == 0);
227 assert(thread);
228
229 if (_status == Idle)
230 return;
231
232 assert(_status == BaseSimpleCPU::Running);
233
234 // just change status to Idle... if status != Running,
235 // completeInst() will not initiate fetch of next instruction.
236
237 notIdleFraction--;
238 _status = Idle;
239}
240
241bool
242TimingSimpleCPU::handleReadPacket(PacketPtr pkt)
243{
244 RequestPtr req = pkt->req;
245 if (req->isMmappedIpr()) {
246 Cycles delay = TheISA::handleIprRead(thread->getTC(), pkt);
247 new IprEvent(pkt, this, clockEdge(delay));
248 _status = DcacheWaitResponse;
249 dcache_pkt = NULL;
250 } else if (!dcachePort.sendTimingReq(pkt)) {
251 _status = DcacheRetry;
252 dcache_pkt = pkt;
253 } else {
254 _status = DcacheWaitResponse;
255 // memory system takes ownership of packet
256 dcache_pkt = NULL;
257 }
258 return dcache_pkt == NULL;
259}
260
261void
262TimingSimpleCPU::sendData(RequestPtr req, uint8_t *data, uint64_t *res,
263 bool read)
264{
265 PacketPtr pkt;
266 buildPacket(pkt, req, read);
267 pkt->dataDynamicArray<uint8_t>(data);
268 if (req->getFlags().isSet(Request::NO_ACCESS)) {
269 assert(!dcache_pkt);
270 pkt->makeResponse();
271 completeDataAccess(pkt);
272 } else if (read) {
273 handleReadPacket(pkt);
274 } else {
275 bool do_access = true; // flag to suppress cache access
276
277 if (req->isLLSC()) {
278 do_access = TheISA::handleLockedWrite(thread, req);
279 } else if (req->isCondSwap()) {
280 assert(res);
281 req->setExtraData(*res);
282 }
283
284 if (do_access) {
285 dcache_pkt = pkt;
286 handleWritePacket();
287 } else {
288 _status = DcacheWaitResponse;
289 completeDataAccess(pkt);
290 }
291 }
292}
293
294void
295TimingSimpleCPU::sendSplitData(RequestPtr req1, RequestPtr req2,
296 RequestPtr req, uint8_t *data, bool read)
297{
298 PacketPtr pkt1, pkt2;
299 buildSplitPacket(pkt1, pkt2, req1, req2, req, data, read);
300 if (req->getFlags().isSet(Request::NO_ACCESS)) {
301 assert(!dcache_pkt);
302 pkt1->makeResponse();
303 completeDataAccess(pkt1);
304 } else if (read) {
305 SplitFragmentSenderState * send_state =
306 dynamic_cast<SplitFragmentSenderState *>(pkt1->senderState);
307 if (handleReadPacket(pkt1)) {
308 send_state->clearFromParent();
309 send_state = dynamic_cast<SplitFragmentSenderState *>(
310 pkt2->senderState);
311 if (handleReadPacket(pkt2)) {
312 send_state->clearFromParent();
313 }
314 }
315 } else {
316 dcache_pkt = pkt1;
317 SplitFragmentSenderState * send_state =
318 dynamic_cast<SplitFragmentSenderState *>(pkt1->senderState);
319 if (handleWritePacket()) {
320 send_state->clearFromParent();
321 dcache_pkt = pkt2;
322 send_state = dynamic_cast<SplitFragmentSenderState *>(
323 pkt2->senderState);
324 if (handleWritePacket()) {
325 send_state->clearFromParent();
326 }
327 }
328 }
329}
330
331void
332TimingSimpleCPU::translationFault(Fault fault)
333{
334 // fault may be NoFault in cases where a fault is suppressed,
335 // for instance prefetches.
336 numCycles += curCycle() - previousCycle;
337 previousCycle = curCycle();
338
339 if (traceData) {
340 // Since there was a fault, we shouldn't trace this instruction.
341 delete traceData;
342 traceData = NULL;
343 }
344
345 postExecute();
346
| 179}
180
181
182void
183TimingSimpleCPU::takeOverFrom(BaseCPU *oldCPU)
184{
185 BaseSimpleCPU::takeOverFrom(oldCPU);
186
187 // if any of this CPU's ThreadContexts are active, mark the CPU as
188 // running and schedule its tick event.
189 for (int i = 0; i < threadContexts.size(); ++i) {
190 ThreadContext *tc = threadContexts[i];
191 if (tc->status() == ThreadContext::Active &&
192 _status != BaseSimpleCPU::Running) {
193 _status = BaseSimpleCPU::Running;
194 break;
195 }
196 }
197
198 if (_status != BaseSimpleCPU::Running) {
199 _status = Idle;
200 }
201 assert(threadContexts.size() == 1);
202 previousCycle = curCycle();
203}
204
205
206void
207TimingSimpleCPU::activateContext(ThreadID thread_num, Cycles delay)
208{
209 DPRINTF(SimpleCPU, "ActivateContext %d (%d cycles)\n", thread_num, delay);
210
211 assert(thread_num == 0);
212 assert(thread);
213
214 assert(_status == Idle);
215
216 notIdleFraction++;
217 _status = BaseSimpleCPU::Running;
218
219 // kick things off by initiating the fetch of the next instruction
220 schedule(fetchEvent, clockEdge(delay));
221}
222
223
224void
225TimingSimpleCPU::suspendContext(ThreadID thread_num)
226{
227 DPRINTF(SimpleCPU, "SuspendContext %d\n", thread_num);
228
229 assert(thread_num == 0);
230 assert(thread);
231
232 if (_status == Idle)
233 return;
234
235 assert(_status == BaseSimpleCPU::Running);
236
237 // just change status to Idle... if status != Running,
238 // completeInst() will not initiate fetch of next instruction.
239
240 notIdleFraction--;
241 _status = Idle;
242}
243
244bool
245TimingSimpleCPU::handleReadPacket(PacketPtr pkt)
246{
247 RequestPtr req = pkt->req;
248 if (req->isMmappedIpr()) {
249 Cycles delay = TheISA::handleIprRead(thread->getTC(), pkt);
250 new IprEvent(pkt, this, clockEdge(delay));
251 _status = DcacheWaitResponse;
252 dcache_pkt = NULL;
253 } else if (!dcachePort.sendTimingReq(pkt)) {
254 _status = DcacheRetry;
255 dcache_pkt = pkt;
256 } else {
257 _status = DcacheWaitResponse;
258 // memory system takes ownership of packet
259 dcache_pkt = NULL;
260 }
261 return dcache_pkt == NULL;
262}
263
264void
265TimingSimpleCPU::sendData(RequestPtr req, uint8_t *data, uint64_t *res,
266 bool read)
267{
268 PacketPtr pkt;
269 buildPacket(pkt, req, read);
270 pkt->dataDynamicArray<uint8_t>(data);
271 if (req->getFlags().isSet(Request::NO_ACCESS)) {
272 assert(!dcache_pkt);
273 pkt->makeResponse();
274 completeDataAccess(pkt);
275 } else if (read) {
276 handleReadPacket(pkt);
277 } else {
278 bool do_access = true; // flag to suppress cache access
279
280 if (req->isLLSC()) {
281 do_access = TheISA::handleLockedWrite(thread, req);
282 } else if (req->isCondSwap()) {
283 assert(res);
284 req->setExtraData(*res);
285 }
286
287 if (do_access) {
288 dcache_pkt = pkt;
289 handleWritePacket();
290 } else {
291 _status = DcacheWaitResponse;
292 completeDataAccess(pkt);
293 }
294 }
295}
296
297void
298TimingSimpleCPU::sendSplitData(RequestPtr req1, RequestPtr req2,
299 RequestPtr req, uint8_t *data, bool read)
300{
301 PacketPtr pkt1, pkt2;
302 buildSplitPacket(pkt1, pkt2, req1, req2, req, data, read);
303 if (req->getFlags().isSet(Request::NO_ACCESS)) {
304 assert(!dcache_pkt);
305 pkt1->makeResponse();
306 completeDataAccess(pkt1);
307 } else if (read) {
308 SplitFragmentSenderState * send_state =
309 dynamic_cast<SplitFragmentSenderState *>(pkt1->senderState);
310 if (handleReadPacket(pkt1)) {
311 send_state->clearFromParent();
312 send_state = dynamic_cast<SplitFragmentSenderState *>(
313 pkt2->senderState);
314 if (handleReadPacket(pkt2)) {
315 send_state->clearFromParent();
316 }
317 }
318 } else {
319 dcache_pkt = pkt1;
320 SplitFragmentSenderState * send_state =
321 dynamic_cast<SplitFragmentSenderState *>(pkt1->senderState);
322 if (handleWritePacket()) {
323 send_state->clearFromParent();
324 dcache_pkt = pkt2;
325 send_state = dynamic_cast<SplitFragmentSenderState *>(
326 pkt2->senderState);
327 if (handleWritePacket()) {
328 send_state->clearFromParent();
329 }
330 }
331 }
332}
333
334void
335TimingSimpleCPU::translationFault(Fault fault)
336{
337 // fault may be NoFault in cases where a fault is suppressed,
338 // for instance prefetches.
339 numCycles += curCycle() - previousCycle;
340 previousCycle = curCycle();
341
342 if (traceData) {
343 // Since there was a fault, we shouldn't trace this instruction.
344 delete traceData;
345 traceData = NULL;
346 }
347
348 postExecute();
349
|
347 if (getDrainState() == Drainable::Draining) {
348 advancePC(fault);
349 completeDrain();
350 } else {
351 advanceInst(fault);
352 }
| 350 advanceInst(fault);
|
353}
354
355void
356TimingSimpleCPU::buildPacket(PacketPtr &pkt, RequestPtr req, bool read)
357{
358 MemCmd cmd;
359 if (read) {
360 cmd = MemCmd::ReadReq;
361 if (req->isLLSC())
362 cmd = MemCmd::LoadLockedReq;
363 } else {
364 cmd = MemCmd::WriteReq;
365 if (req->isLLSC()) {
366 cmd = MemCmd::StoreCondReq;
367 } else if (req->isSwap()) {
368 cmd = MemCmd::SwapReq;
369 }
370 }
371 pkt = new Packet(req, cmd);
372}
373
374void
375TimingSimpleCPU::buildSplitPacket(PacketPtr &pkt1, PacketPtr &pkt2,
376 RequestPtr req1, RequestPtr req2, RequestPtr req,
377 uint8_t *data, bool read)
378{
379 pkt1 = pkt2 = NULL;
380
381 assert(!req1->isMmappedIpr() && !req2->isMmappedIpr());
382
383 if (req->getFlags().isSet(Request::NO_ACCESS)) {
384 buildPacket(pkt1, req, read);
385 return;
386 }
387
388 buildPacket(pkt1, req1, read);
389 buildPacket(pkt2, req2, read);
390
391 req->setPhys(req1->getPaddr(), req->getSize(), req1->getFlags(), dataMasterId());
392 PacketPtr pkt = new Packet(req, pkt1->cmd.responseCommand());
393
394 pkt->dataDynamicArray<uint8_t>(data);
395 pkt1->dataStatic<uint8_t>(data);
396 pkt2->dataStatic<uint8_t>(data + req1->getSize());
397
398 SplitMainSenderState * main_send_state = new SplitMainSenderState;
399 pkt->senderState = main_send_state;
400 main_send_state->fragments[0] = pkt1;
401 main_send_state->fragments[1] = pkt2;
402 main_send_state->outstanding = 2;
403 pkt1->senderState = new SplitFragmentSenderState(pkt, 0);
404 pkt2->senderState = new SplitFragmentSenderState(pkt, 1);
405}
406
407Fault
408TimingSimpleCPU::readMem(Addr addr, uint8_t *data,
409 unsigned size, unsigned flags)
410{
411 Fault fault;
412 const int asid = 0;
413 const ThreadID tid = 0;
414 const Addr pc = thread->instAddr();
415 unsigned block_size = dcachePort.peerBlockSize();
416 BaseTLB::Mode mode = BaseTLB::Read;
417
418 if (traceData) {
419 traceData->setAddr(addr);
420 }
421
422 RequestPtr req = new Request(asid, addr, size,
423 flags, dataMasterId(), pc, _cpuId, tid);
424
425 Addr split_addr = roundDown(addr + size - 1, block_size);
426 assert(split_addr <= addr || split_addr - addr < block_size);
427
428 _status = DTBWaitResponse;
429 if (split_addr > addr) {
430 RequestPtr req1, req2;
431 assert(!req->isLLSC() && !req->isSwap());
432 req->splitOnVaddr(split_addr, req1, req2);
433
434 WholeTranslationState *state =
435 new WholeTranslationState(req, req1, req2, new uint8_t[size],
436 NULL, mode);
437 DataTranslation<TimingSimpleCPU *> *trans1 =
438 new DataTranslation<TimingSimpleCPU *>(this, state, 0);
439 DataTranslation<TimingSimpleCPU *> *trans2 =
440 new DataTranslation<TimingSimpleCPU *>(this, state, 1);
441
442 thread->dtb->translateTiming(req1, tc, trans1, mode);
443 thread->dtb->translateTiming(req2, tc, trans2, mode);
444 } else {
445 WholeTranslationState *state =
446 new WholeTranslationState(req, new uint8_t[size], NULL, mode);
447 DataTranslation<TimingSimpleCPU *> *translation
448 = new DataTranslation<TimingSimpleCPU *>(this, state);
449 thread->dtb->translateTiming(req, tc, translation, mode);
450 }
451
452 return NoFault;
453}
454
455bool
456TimingSimpleCPU::handleWritePacket()
457{
458 RequestPtr req = dcache_pkt->req;
459 if (req->isMmappedIpr()) {
460 Cycles delay = TheISA::handleIprWrite(thread->getTC(), dcache_pkt);
461 new IprEvent(dcache_pkt, this, clockEdge(delay));
462 _status = DcacheWaitResponse;
463 dcache_pkt = NULL;
464 } else if (!dcachePort.sendTimingReq(dcache_pkt)) {
465 _status = DcacheRetry;
466 } else {
467 _status = DcacheWaitResponse;
468 // memory system takes ownership of packet
469 dcache_pkt = NULL;
470 }
471 return dcache_pkt == NULL;
472}
473
474Fault
475TimingSimpleCPU::writeMem(uint8_t *data, unsigned size,
476 Addr addr, unsigned flags, uint64_t *res)
477{
478 uint8_t *newData = new uint8_t[size];
479 memcpy(newData, data, size);
480
481 const int asid = 0;
482 const ThreadID tid = 0;
483 const Addr pc = thread->instAddr();
484 unsigned block_size = dcachePort.peerBlockSize();
485 BaseTLB::Mode mode = BaseTLB::Write;
486
487 if (traceData) {
488 traceData->setAddr(addr);
489 }
490
491 RequestPtr req = new Request(asid, addr, size,
492 flags, dataMasterId(), pc, _cpuId, tid);
493
494 Addr split_addr = roundDown(addr + size - 1, block_size);
495 assert(split_addr <= addr || split_addr - addr < block_size);
496
497 _status = DTBWaitResponse;
498 if (split_addr > addr) {
499 RequestPtr req1, req2;
500 assert(!req->isLLSC() && !req->isSwap());
501 req->splitOnVaddr(split_addr, req1, req2);
502
503 WholeTranslationState *state =
504 new WholeTranslationState(req, req1, req2, newData, res, mode);
505 DataTranslation<TimingSimpleCPU *> *trans1 =
506 new DataTranslation<TimingSimpleCPU *>(this, state, 0);
507 DataTranslation<TimingSimpleCPU *> *trans2 =
508 new DataTranslation<TimingSimpleCPU *>(this, state, 1);
509
510 thread->dtb->translateTiming(req1, tc, trans1, mode);
511 thread->dtb->translateTiming(req2, tc, trans2, mode);
512 } else {
513 WholeTranslationState *state =
514 new WholeTranslationState(req, newData, res, mode);
515 DataTranslation<TimingSimpleCPU *> *translation =
516 new DataTranslation<TimingSimpleCPU *>(this, state);
517 thread->dtb->translateTiming(req, tc, translation, mode);
518 }
519
520 // Translation faults will be returned via finishTranslation()
521 return NoFault;
522}
523
524
525void
526TimingSimpleCPU::finishTranslation(WholeTranslationState *state)
527{
528 _status = BaseSimpleCPU::Running;
529
530 if (state->getFault() != NoFault) {
531 if (state->isPrefetch()) {
532 state->setNoFault();
533 }
534 delete [] state->data;
535 state->deleteReqs();
536 translationFault(state->getFault());
537 } else {
538 if (!state->isSplit) {
539 sendData(state->mainReq, state->data, state->res,
540 state->mode == BaseTLB::Read);
541 } else {
542 sendSplitData(state->sreqLow, state->sreqHigh, state->mainReq,
543 state->data, state->mode == BaseTLB::Read);
544 }
545 }
546
547 delete state;
548}
549
550
551void
552TimingSimpleCPU::fetch()
553{
554 DPRINTF(SimpleCPU, "Fetch\n");
555
556 if (!curStaticInst || !curStaticInst->isDelayedCommit())
557 checkForInterrupts();
558
559 checkPcEventQueue();
560
561 // We must have just got suspended by a PC event
562 if (_status == Idle)
563 return;
564
565 TheISA::PCState pcState = thread->pcState();
566 bool needToFetch = !isRomMicroPC(pcState.microPC()) && !curMacroStaticInst;
567
568 if (needToFetch) {
569 _status = BaseSimpleCPU::Running;
570 Request *ifetch_req = new Request();
571 ifetch_req->setThreadContext(_cpuId, /* thread ID */ 0);
572 setupFetchRequest(ifetch_req);
573 DPRINTF(SimpleCPU, "Translating address %#x\n", ifetch_req->getVaddr());
574 thread->itb->translateTiming(ifetch_req, tc, &fetchTranslation,
575 BaseTLB::Execute);
576 } else {
577 _status = IcacheWaitResponse;
578 completeIfetch(NULL);
579
580 numCycles += curCycle() - previousCycle;
581 previousCycle = curCycle();
582 }
583}
584
585
586void
587TimingSimpleCPU::sendFetch(Fault fault, RequestPtr req, ThreadContext *tc)
588{
589 if (fault == NoFault) {
590 DPRINTF(SimpleCPU, "Sending fetch for addr %#x(pa: %#x)\n",
591 req->getVaddr(), req->getPaddr());
592 ifetch_pkt = new Packet(req, MemCmd::ReadReq);
593 ifetch_pkt->dataStatic(&inst);
594 DPRINTF(SimpleCPU, " -- pkt addr: %#x\n", ifetch_pkt->getAddr());
595
596 if (!icachePort.sendTimingReq(ifetch_pkt)) {
597 // Need to wait for retry
598 _status = IcacheRetry;
599 } else {
600 // Need to wait for cache to respond
601 _status = IcacheWaitResponse;
602 // ownership of packet transferred to memory system
603 ifetch_pkt = NULL;
604 }
605 } else {
606 DPRINTF(SimpleCPU, "Translation of addr %#x faulted\n", req->getVaddr());
607 delete req;
608 // fetch fault: advance directly to next instruction (fault handler)
609 _status = BaseSimpleCPU::Running;
610 advanceInst(fault);
611 }
612
613 numCycles += curCycle() - previousCycle;
614 previousCycle = curCycle();
615}
616
617
618void
619TimingSimpleCPU::advanceInst(Fault fault)
620{
| 351}
352
353void
354TimingSimpleCPU::buildPacket(PacketPtr &pkt, RequestPtr req, bool read)
355{
356 MemCmd cmd;
357 if (read) {
358 cmd = MemCmd::ReadReq;
359 if (req->isLLSC())
360 cmd = MemCmd::LoadLockedReq;
361 } else {
362 cmd = MemCmd::WriteReq;
363 if (req->isLLSC()) {
364 cmd = MemCmd::StoreCondReq;
365 } else if (req->isSwap()) {
366 cmd = MemCmd::SwapReq;
367 }
368 }
369 pkt = new Packet(req, cmd);
370}
371
372void
373TimingSimpleCPU::buildSplitPacket(PacketPtr &pkt1, PacketPtr &pkt2,
374 RequestPtr req1, RequestPtr req2, RequestPtr req,
375 uint8_t *data, bool read)
376{
377 pkt1 = pkt2 = NULL;
378
379 assert(!req1->isMmappedIpr() && !req2->isMmappedIpr());
380
381 if (req->getFlags().isSet(Request::NO_ACCESS)) {
382 buildPacket(pkt1, req, read);
383 return;
384 }
385
386 buildPacket(pkt1, req1, read);
387 buildPacket(pkt2, req2, read);
388
389 req->setPhys(req1->getPaddr(), req->getSize(), req1->getFlags(), dataMasterId());
390 PacketPtr pkt = new Packet(req, pkt1->cmd.responseCommand());
391
392 pkt->dataDynamicArray<uint8_t>(data);
393 pkt1->dataStatic<uint8_t>(data);
394 pkt2->dataStatic<uint8_t>(data + req1->getSize());
395
396 SplitMainSenderState * main_send_state = new SplitMainSenderState;
397 pkt->senderState = main_send_state;
398 main_send_state->fragments[0] = pkt1;
399 main_send_state->fragments[1] = pkt2;
400 main_send_state->outstanding = 2;
401 pkt1->senderState = new SplitFragmentSenderState(pkt, 0);
402 pkt2->senderState = new SplitFragmentSenderState(pkt, 1);
403}
404
405Fault
406TimingSimpleCPU::readMem(Addr addr, uint8_t *data,
407 unsigned size, unsigned flags)
408{
409 Fault fault;
410 const int asid = 0;
411 const ThreadID tid = 0;
412 const Addr pc = thread->instAddr();
413 unsigned block_size = dcachePort.peerBlockSize();
414 BaseTLB::Mode mode = BaseTLB::Read;
415
416 if (traceData) {
417 traceData->setAddr(addr);
418 }
419
420 RequestPtr req = new Request(asid, addr, size,
421 flags, dataMasterId(), pc, _cpuId, tid);
422
423 Addr split_addr = roundDown(addr + size - 1, block_size);
424 assert(split_addr <= addr || split_addr - addr < block_size);
425
426 _status = DTBWaitResponse;
427 if (split_addr > addr) {
428 RequestPtr req1, req2;
429 assert(!req->isLLSC() && !req->isSwap());
430 req->splitOnVaddr(split_addr, req1, req2);
431
432 WholeTranslationState *state =
433 new WholeTranslationState(req, req1, req2, new uint8_t[size],
434 NULL, mode);
435 DataTranslation<TimingSimpleCPU *> *trans1 =
436 new DataTranslation<TimingSimpleCPU *>(this, state, 0);
437 DataTranslation<TimingSimpleCPU *> *trans2 =
438 new DataTranslation<TimingSimpleCPU *>(this, state, 1);
439
440 thread->dtb->translateTiming(req1, tc, trans1, mode);
441 thread->dtb->translateTiming(req2, tc, trans2, mode);
442 } else {
443 WholeTranslationState *state =
444 new WholeTranslationState(req, new uint8_t[size], NULL, mode);
445 DataTranslation<TimingSimpleCPU *> *translation
446 = new DataTranslation<TimingSimpleCPU *>(this, state);
447 thread->dtb->translateTiming(req, tc, translation, mode);
448 }
449
450 return NoFault;
451}
452
453bool
454TimingSimpleCPU::handleWritePacket()
455{
456 RequestPtr req = dcache_pkt->req;
457 if (req->isMmappedIpr()) {
458 Cycles delay = TheISA::handleIprWrite(thread->getTC(), dcache_pkt);
459 new IprEvent(dcache_pkt, this, clockEdge(delay));
460 _status = DcacheWaitResponse;
461 dcache_pkt = NULL;
462 } else if (!dcachePort.sendTimingReq(dcache_pkt)) {
463 _status = DcacheRetry;
464 } else {
465 _status = DcacheWaitResponse;
466 // memory system takes ownership of packet
467 dcache_pkt = NULL;
468 }
469 return dcache_pkt == NULL;
470}
471
472Fault
473TimingSimpleCPU::writeMem(uint8_t *data, unsigned size,
474 Addr addr, unsigned flags, uint64_t *res)
475{
476 uint8_t *newData = new uint8_t[size];
477 memcpy(newData, data, size);
478
479 const int asid = 0;
480 const ThreadID tid = 0;
481 const Addr pc = thread->instAddr();
482 unsigned block_size = dcachePort.peerBlockSize();
483 BaseTLB::Mode mode = BaseTLB::Write;
484
485 if (traceData) {
486 traceData->setAddr(addr);
487 }
488
489 RequestPtr req = new Request(asid, addr, size,
490 flags, dataMasterId(), pc, _cpuId, tid);
491
492 Addr split_addr = roundDown(addr + size - 1, block_size);
493 assert(split_addr <= addr || split_addr - addr < block_size);
494
495 _status = DTBWaitResponse;
496 if (split_addr > addr) {
497 RequestPtr req1, req2;
498 assert(!req->isLLSC() && !req->isSwap());
499 req->splitOnVaddr(split_addr, req1, req2);
500
501 WholeTranslationState *state =
502 new WholeTranslationState(req, req1, req2, newData, res, mode);
503 DataTranslation<TimingSimpleCPU *> *trans1 =
504 new DataTranslation<TimingSimpleCPU *>(this, state, 0);
505 DataTranslation<TimingSimpleCPU *> *trans2 =
506 new DataTranslation<TimingSimpleCPU *>(this, state, 1);
507
508 thread->dtb->translateTiming(req1, tc, trans1, mode);
509 thread->dtb->translateTiming(req2, tc, trans2, mode);
510 } else {
511 WholeTranslationState *state =
512 new WholeTranslationState(req, newData, res, mode);
513 DataTranslation<TimingSimpleCPU *> *translation =
514 new DataTranslation<TimingSimpleCPU *>(this, state);
515 thread->dtb->translateTiming(req, tc, translation, mode);
516 }
517
518 // Translation faults will be returned via finishTranslation()
519 return NoFault;
520}
521
522
523void
524TimingSimpleCPU::finishTranslation(WholeTranslationState *state)
525{
526 _status = BaseSimpleCPU::Running;
527
528 if (state->getFault() != NoFault) {
529 if (state->isPrefetch()) {
530 state->setNoFault();
531 }
532 delete [] state->data;
533 state->deleteReqs();
534 translationFault(state->getFault());
535 } else {
536 if (!state->isSplit) {
537 sendData(state->mainReq, state->data, state->res,
538 state->mode == BaseTLB::Read);
539 } else {
540 sendSplitData(state->sreqLow, state->sreqHigh, state->mainReq,
541 state->data, state->mode == BaseTLB::Read);
542 }
543 }
544
545 delete state;
546}
547
548
549void
550TimingSimpleCPU::fetch()
551{
552 DPRINTF(SimpleCPU, "Fetch\n");
553
554 if (!curStaticInst || !curStaticInst->isDelayedCommit())
555 checkForInterrupts();
556
557 checkPcEventQueue();
558
559 // We must have just got suspended by a PC event
560 if (_status == Idle)
561 return;
562
563 TheISA::PCState pcState = thread->pcState();
564 bool needToFetch = !isRomMicroPC(pcState.microPC()) && !curMacroStaticInst;
565
566 if (needToFetch) {
567 _status = BaseSimpleCPU::Running;
568 Request *ifetch_req = new Request();
569 ifetch_req->setThreadContext(_cpuId, /* thread ID */ 0);
570 setupFetchRequest(ifetch_req);
571 DPRINTF(SimpleCPU, "Translating address %#x\n", ifetch_req->getVaddr());
572 thread->itb->translateTiming(ifetch_req, tc, &fetchTranslation,
573 BaseTLB::Execute);
574 } else {
575 _status = IcacheWaitResponse;
576 completeIfetch(NULL);
577
578 numCycles += curCycle() - previousCycle;
579 previousCycle = curCycle();
580 }
581}
582
583
584void
585TimingSimpleCPU::sendFetch(Fault fault, RequestPtr req, ThreadContext *tc)
586{
587 if (fault == NoFault) {
588 DPRINTF(SimpleCPU, "Sending fetch for addr %#x(pa: %#x)\n",
589 req->getVaddr(), req->getPaddr());
590 ifetch_pkt = new Packet(req, MemCmd::ReadReq);
591 ifetch_pkt->dataStatic(&inst);
592 DPRINTF(SimpleCPU, " -- pkt addr: %#x\n", ifetch_pkt->getAddr());
593
594 if (!icachePort.sendTimingReq(ifetch_pkt)) {
595 // Need to wait for retry
596 _status = IcacheRetry;
597 } else {
598 // Need to wait for cache to respond
599 _status = IcacheWaitResponse;
600 // ownership of packet transferred to memory system
601 ifetch_pkt = NULL;
602 }
603 } else {
604 DPRINTF(SimpleCPU, "Translation of addr %#x faulted\n", req->getVaddr());
605 delete req;
606 // fetch fault: advance directly to next instruction (fault handler)
607 _status = BaseSimpleCPU::Running;
608 advanceInst(fault);
609 }
610
611 numCycles += curCycle() - previousCycle;
612 previousCycle = curCycle();
613}
614
615
616void
617TimingSimpleCPU::advanceInst(Fault fault)
618{
|
621
| |
622 if (_status == Faulting)
623 return;
624
625 if (fault != NoFault) {
626 advancePC(fault);
627 DPRINTF(SimpleCPU, "Fault occured, scheduling fetch event\n");
628 reschedule(fetchEvent, nextCycle(), true);
629 _status = Faulting;
630 return;
631 }
632
633
634 if (!stayAtPC)
635 advancePC(fault);
636
| 619 if (_status == Faulting)
620 return;
621
622 if (fault != NoFault) {
623 advancePC(fault);
624 DPRINTF(SimpleCPU, "Fault occured, scheduling fetch event\n");
625 reschedule(fetchEvent, nextCycle(), true);
626 _status = Faulting;
627 return;
628 }
629
630
631 if (!stayAtPC)
632 advancePC(fault);
633
|
| 634 if (tryCompleteDrain())
635 return;
636
|
637 if (_status == BaseSimpleCPU::Running) {
638 // kick off fetch of next instruction... callback from icache
639 // response will cause that instruction to be executed,
640 // keeping the CPU running.
641 fetch();
642 }
643}
644
645
646void
647TimingSimpleCPU::completeIfetch(PacketPtr pkt)
648{
649 DPRINTF(SimpleCPU, "Complete ICache Fetch for addr %#x\n", pkt ?
650 pkt->getAddr() : 0);
651
652 // received a response from the icache: execute the received
653 // instruction
654
655 assert(!pkt || !pkt->isError());
656 assert(_status == IcacheWaitResponse);
657
658 _status = BaseSimpleCPU::Running;
659
660 numCycles += curCycle() - previousCycle;
661 previousCycle = curCycle();
662
| 637 if (_status == BaseSimpleCPU::Running) {
638 // kick off fetch of next instruction... callback from icache
639 // response will cause that instruction to be executed,
640 // keeping the CPU running.
641 fetch();
642 }
643}
644
645
646void
647TimingSimpleCPU::completeIfetch(PacketPtr pkt)
648{
649 DPRINTF(SimpleCPU, "Complete ICache Fetch for addr %#x\n", pkt ?
650 pkt->getAddr() : 0);
651
652 // received a response from the icache: execute the received
653 // instruction
654
655 assert(!pkt || !pkt->isError());
656 assert(_status == IcacheWaitResponse);
657
658 _status = BaseSimpleCPU::Running;
659
660 numCycles += curCycle() - previousCycle;
661 previousCycle = curCycle();
662
|
663 if (getDrainState() == Drainable::Draining) {
664 if (pkt) {
665 delete pkt->req;
666 delete pkt;
667 }
668
669 completeDrain();
670 return;
671 }
672
| |
673 preExecute();
674 if (curStaticInst && curStaticInst->isMemRef()) {
675 // load or store: just send to dcache
676 Fault fault = curStaticInst->initiateAcc(this, traceData);
677
678 // If we're not running now the instruction will complete in a dcache
679 // response callback or the instruction faulted and has started an
680 // ifetch
681 if (_status == BaseSimpleCPU::Running) {
682 if (fault != NoFault && traceData) {
683 // If there was a fault, we shouldn't trace this instruction.
684 delete traceData;
685 traceData = NULL;
686 }
687
688 postExecute();
689 // @todo remove me after debugging with legion done
690 if (curStaticInst && (!curStaticInst->isMicroop() ||
691 curStaticInst->isFirstMicroop()))
692 instCnt++;
693 advanceInst(fault);
694 }
695 } else if (curStaticInst) {
696 // non-memory instruction: execute completely now
697 Fault fault = curStaticInst->execute(this, traceData);
698
699 // keep an instruction count
700 if (fault == NoFault)
701 countInst();
702 else if (traceData && !DTRACE(ExecFaulting)) {
703 delete traceData;
704 traceData = NULL;
705 }
706
707 postExecute();
708 // @todo remove me after debugging with legion done
709 if (curStaticInst && (!curStaticInst->isMicroop() ||
710 curStaticInst->isFirstMicroop()))
711 instCnt++;
712 advanceInst(fault);
713 } else {
714 advanceInst(NoFault);
715 }
716
717 if (pkt) {
718 delete pkt->req;
719 delete pkt;
720 }
721}
722
723void
724TimingSimpleCPU::IcachePort::ITickEvent::process()
725{
726 cpu->completeIfetch(pkt);
727}
728
729bool
730TimingSimpleCPU::IcachePort::recvTimingResp(PacketPtr pkt)
731{
732 DPRINTF(SimpleCPU, "Received timing response %#x\n", pkt->getAddr());
733 // delay processing of returned data until next CPU clock edge
734 Tick next_tick = cpu->nextCycle();
735
736 if (next_tick == curTick())
737 cpu->completeIfetch(pkt);
738 else
739 tickEvent.schedule(pkt, next_tick);
740
741 return true;
742}
743
744void
745TimingSimpleCPU::IcachePort::recvRetry()
746{
747 // we shouldn't get a retry unless we have a packet that we're
748 // waiting to transmit
749 assert(cpu->ifetch_pkt != NULL);
750 assert(cpu->_status == IcacheRetry);
751 PacketPtr tmp = cpu->ifetch_pkt;
752 if (sendTimingReq(tmp)) {
753 cpu->_status = IcacheWaitResponse;
754 cpu->ifetch_pkt = NULL;
755 }
756}
757
758void
759TimingSimpleCPU::completeDataAccess(PacketPtr pkt)
760{
761 // received a response from the dcache: complete the load or store
762 // instruction
763 assert(!pkt->isError());
764 assert(_status == DcacheWaitResponse || _status == DTBWaitResponse ||
765 pkt->req->getFlags().isSet(Request::NO_ACCESS));
766
767 numCycles += curCycle() - previousCycle;
768 previousCycle = curCycle();
769
770 if (pkt->senderState) {
771 SplitFragmentSenderState * send_state =
772 dynamic_cast<SplitFragmentSenderState *>(pkt->senderState);
773 assert(send_state);
774 delete pkt->req;
775 delete pkt;
776 PacketPtr big_pkt = send_state->bigPkt;
777 delete send_state;
778
779 SplitMainSenderState * main_send_state =
780 dynamic_cast<SplitMainSenderState *>(big_pkt->senderState);
781 assert(main_send_state);
782 // Record the fact that this packet is no longer outstanding.
783 assert(main_send_state->outstanding != 0);
784 main_send_state->outstanding--;
785
786 if (main_send_state->outstanding) {
787 return;
788 } else {
789 delete main_send_state;
790 big_pkt->senderState = NULL;
791 pkt = big_pkt;
792 }
793 }
794
795 _status = BaseSimpleCPU::Running;
796
797 Fault fault = curStaticInst->completeAcc(pkt, this, traceData);
798
799 // keep an instruction count
800 if (fault == NoFault)
801 countInst();
802 else if (traceData) {
803 // If there was a fault, we shouldn't trace this instruction.
804 delete traceData;
805 traceData = NULL;
806 }
807
808 // the locked flag may be cleared on the response packet, so check
809 // pkt->req and not pkt to see if it was a load-locked
810 if (pkt->isRead() && pkt->req->isLLSC()) {
811 TheISA::handleLockedRead(thread, pkt->req);
812 }
813
814 delete pkt->req;
815 delete pkt;
816
817 postExecute();
818
| 663 preExecute();
664 if (curStaticInst && curStaticInst->isMemRef()) {
665 // load or store: just send to dcache
666 Fault fault = curStaticInst->initiateAcc(this, traceData);
667
668 // If we're not running now the instruction will complete in a dcache
669 // response callback or the instruction faulted and has started an
670 // ifetch
671 if (_status == BaseSimpleCPU::Running) {
672 if (fault != NoFault && traceData) {
673 // If there was a fault, we shouldn't trace this instruction.
674 delete traceData;
675 traceData = NULL;
676 }
677
678 postExecute();
679 // @todo remove me after debugging with legion done
680 if (curStaticInst && (!curStaticInst->isMicroop() ||
681 curStaticInst->isFirstMicroop()))
682 instCnt++;
683 advanceInst(fault);
684 }
685 } else if (curStaticInst) {
686 // non-memory instruction: execute completely now
687 Fault fault = curStaticInst->execute(this, traceData);
688
689 // keep an instruction count
690 if (fault == NoFault)
691 countInst();
692 else if (traceData && !DTRACE(ExecFaulting)) {
693 delete traceData;
694 traceData = NULL;
695 }
696
697 postExecute();
698 // @todo remove me after debugging with legion done
699 if (curStaticInst && (!curStaticInst->isMicroop() ||
700 curStaticInst->isFirstMicroop()))
701 instCnt++;
702 advanceInst(fault);
703 } else {
704 advanceInst(NoFault);
705 }
706
707 if (pkt) {
708 delete pkt->req;
709 delete pkt;
710 }
711}
712
713void
714TimingSimpleCPU::IcachePort::ITickEvent::process()
715{
716 cpu->completeIfetch(pkt);
717}
718
719bool
720TimingSimpleCPU::IcachePort::recvTimingResp(PacketPtr pkt)
721{
722 DPRINTF(SimpleCPU, "Received timing response %#x\n", pkt->getAddr());
723 // delay processing of returned data until next CPU clock edge
724 Tick next_tick = cpu->nextCycle();
725
726 if (next_tick == curTick())
727 cpu->completeIfetch(pkt);
728 else
729 tickEvent.schedule(pkt, next_tick);
730
731 return true;
732}
733
734void
735TimingSimpleCPU::IcachePort::recvRetry()
736{
737 // we shouldn't get a retry unless we have a packet that we're
738 // waiting to transmit
739 assert(cpu->ifetch_pkt != NULL);
740 assert(cpu->_status == IcacheRetry);
741 PacketPtr tmp = cpu->ifetch_pkt;
742 if (sendTimingReq(tmp)) {
743 cpu->_status = IcacheWaitResponse;
744 cpu->ifetch_pkt = NULL;
745 }
746}
747
748void
749TimingSimpleCPU::completeDataAccess(PacketPtr pkt)
750{
751 // received a response from the dcache: complete the load or store
752 // instruction
753 assert(!pkt->isError());
754 assert(_status == DcacheWaitResponse || _status == DTBWaitResponse ||
755 pkt->req->getFlags().isSet(Request::NO_ACCESS));
756
757 numCycles += curCycle() - previousCycle;
758 previousCycle = curCycle();
759
760 if (pkt->senderState) {
761 SplitFragmentSenderState * send_state =
762 dynamic_cast<SplitFragmentSenderState *>(pkt->senderState);
763 assert(send_state);
764 delete pkt->req;
765 delete pkt;
766 PacketPtr big_pkt = send_state->bigPkt;
767 delete send_state;
768
769 SplitMainSenderState * main_send_state =
770 dynamic_cast<SplitMainSenderState *>(big_pkt->senderState);
771 assert(main_send_state);
772 // Record the fact that this packet is no longer outstanding.
773 assert(main_send_state->outstanding != 0);
774 main_send_state->outstanding--;
775
776 if (main_send_state->outstanding) {
777 return;
778 } else {
779 delete main_send_state;
780 big_pkt->senderState = NULL;
781 pkt = big_pkt;
782 }
783 }
784
785 _status = BaseSimpleCPU::Running;
786
787 Fault fault = curStaticInst->completeAcc(pkt, this, traceData);
788
789 // keep an instruction count
790 if (fault == NoFault)
791 countInst();
792 else if (traceData) {
793 // If there was a fault, we shouldn't trace this instruction.
794 delete traceData;
795 traceData = NULL;
796 }
797
798 // the locked flag may be cleared on the response packet, so check
799 // pkt->req and not pkt to see if it was a load-locked
800 if (pkt->isRead() && pkt->req->isLLSC()) {
801 TheISA::handleLockedRead(thread, pkt->req);
802 }
803
804 delete pkt->req;
805 delete pkt;
806
807 postExecute();
808
|
819 if (getDrainState() == Drainable::Draining) {
820 advancePC(fault);
821 completeDrain();
822
823 return;
824 }
825
| |
826 advanceInst(fault);
827}
828
| 809 advanceInst(fault);
810}
811
|
829
830void
831TimingSimpleCPU::completeDrain()
832{
833 DPRINTF(Drain, "CPU done draining, processing drain event\n");
834 setDrainState(Drainable::Drained);
835 drainManager->signalDrainDone();
836}
837
| |
838bool
839TimingSimpleCPU::DcachePort::recvTimingResp(PacketPtr pkt)
840{
841 // delay processing of returned data until next CPU clock edge
842 Tick next_tick = cpu->nextCycle();
843
844 if (next_tick == curTick()) {
845 cpu->completeDataAccess(pkt);
846 } else {
847 if (!tickEvent.scheduled()) {
848 tickEvent.schedule(pkt, next_tick);
849 } else {
850 // In the case of a split transaction and a cache that is
851 // faster than a CPU we could get two responses before
852 // next_tick expires
853 if (!retryEvent.scheduled())
854 cpu->schedule(retryEvent, next_tick);
855 return false;
856 }
857 }
858
859 return true;
860}
861
862void
863TimingSimpleCPU::DcachePort::DTickEvent::process()
864{
865 cpu->completeDataAccess(pkt);
866}
867
868void
869TimingSimpleCPU::DcachePort::recvRetry()
870{
871 // we shouldn't get a retry unless we have a packet that we're
872 // waiting to transmit
873 assert(cpu->dcache_pkt != NULL);
874 assert(cpu->_status == DcacheRetry);
875 PacketPtr tmp = cpu->dcache_pkt;
876 if (tmp->senderState) {
877 // This is a packet from a split access.
878 SplitFragmentSenderState * send_state =
879 dynamic_cast<SplitFragmentSenderState *>(tmp->senderState);
880 assert(send_state);
881 PacketPtr big_pkt = send_state->bigPkt;
882
883 SplitMainSenderState * main_send_state =
884 dynamic_cast<SplitMainSenderState *>(big_pkt->senderState);
885 assert(main_send_state);
886
887 if (sendTimingReq(tmp)) {
888 // If we were able to send without retrying, record that fact
889 // and try sending the other fragment.
890 send_state->clearFromParent();
891 int other_index = main_send_state->getPendingFragment();
892 if (other_index > 0) {
893 tmp = main_send_state->fragments[other_index];
894 cpu->dcache_pkt = tmp;
895 if ((big_pkt->isRead() && cpu->handleReadPacket(tmp)) ||
896 (big_pkt->isWrite() && cpu->handleWritePacket())) {
897 main_send_state->fragments[other_index] = NULL;
898 }
899 } else {
900 cpu->_status = DcacheWaitResponse;
901 // memory system takes ownership of packet
902 cpu->dcache_pkt = NULL;
903 }
904 }
905 } else if (sendTimingReq(tmp)) {
906 cpu->_status = DcacheWaitResponse;
907 // memory system takes ownership of packet
908 cpu->dcache_pkt = NULL;
909 }
910}
911
912TimingSimpleCPU::IprEvent::IprEvent(Packet *_pkt, TimingSimpleCPU *_cpu,
913 Tick t)
914 : pkt(_pkt), cpu(_cpu)
915{
916 cpu->schedule(this, t);
917}
918
919void
920TimingSimpleCPU::IprEvent::process()
921{
922 cpu->completeDataAccess(pkt);
923}
924
925const char *
926TimingSimpleCPU::IprEvent::description() const
927{
928 return "Timing Simple CPU Delay IPR event";
929}
930
931
932void
933TimingSimpleCPU::printAddr(Addr a)
934{
935 dcachePort.printAddr(a);
936}
937
938
939////////////////////////////////////////////////////////////////////////
940//
941// TimingSimpleCPU Simulation Object
942//
943TimingSimpleCPU *
944TimingSimpleCPUParams::create()
945{
946 numThreads = 1;
947 if (!FullSystem && workload.size() != 1)
948 panic("only one workload allowed");
949 return new TimingSimpleCPU(this);
950}
| 812bool
813TimingSimpleCPU::DcachePort::recvTimingResp(PacketPtr pkt)
814{
815 // delay processing of returned data until next CPU clock edge
816 Tick next_tick = cpu->nextCycle();
817
818 if (next_tick == curTick()) {
819 cpu->completeDataAccess(pkt);
820 } else {
821 if (!tickEvent.scheduled()) {
822 tickEvent.schedule(pkt, next_tick);
823 } else {
824 // In the case of a split transaction and a cache that is
825 // faster than a CPU we could get two responses before
826 // next_tick expires
827 if (!retryEvent.scheduled())
828 cpu->schedule(retryEvent, next_tick);
829 return false;
830 }
831 }
832
833 return true;
834}
835
836void
837TimingSimpleCPU::DcachePort::DTickEvent::process()
838{
839 cpu->completeDataAccess(pkt);
840}
841
842void
843TimingSimpleCPU::DcachePort::recvRetry()
844{
845 // we shouldn't get a retry unless we have a packet that we're
846 // waiting to transmit
847 assert(cpu->dcache_pkt != NULL);
848 assert(cpu->_status == DcacheRetry);
849 PacketPtr tmp = cpu->dcache_pkt;
850 if (tmp->senderState) {
851 // This is a packet from a split access.
852 SplitFragmentSenderState * send_state =
853 dynamic_cast<SplitFragmentSenderState *>(tmp->senderState);
854 assert(send_state);
855 PacketPtr big_pkt = send_state->bigPkt;
856
857 SplitMainSenderState * main_send_state =
858 dynamic_cast<SplitMainSenderState *>(big_pkt->senderState);
859 assert(main_send_state);
860
861 if (sendTimingReq(tmp)) {
862 // If we were able to send without retrying, record that fact
863 // and try sending the other fragment.
864 send_state->clearFromParent();
865 int other_index = main_send_state->getPendingFragment();
866 if (other_index > 0) {
867 tmp = main_send_state->fragments[other_index];
868 cpu->dcache_pkt = tmp;
869 if ((big_pkt->isRead() && cpu->handleReadPacket(tmp)) ||
870 (big_pkt->isWrite() && cpu->handleWritePacket())) {
871 main_send_state->fragments[other_index] = NULL;
872 }
873 } else {
874 cpu->_status = DcacheWaitResponse;
875 // memory system takes ownership of packet
876 cpu->dcache_pkt = NULL;
877 }
878 }
879 } else if (sendTimingReq(tmp)) {
880 cpu->_status = DcacheWaitResponse;
881 // memory system takes ownership of packet
882 cpu->dcache_pkt = NULL;
883 }
884}
885
886TimingSimpleCPU::IprEvent::IprEvent(Packet *_pkt, TimingSimpleCPU *_cpu,
887 Tick t)
888 : pkt(_pkt), cpu(_cpu)
889{
890 cpu->schedule(this, t);
891}
892
893void
894TimingSimpleCPU::IprEvent::process()
895{
896 cpu->completeDataAccess(pkt);
897}
898
899const char *
900TimingSimpleCPU::IprEvent::description() const
901{
902 return "Timing Simple CPU Delay IPR event";
903}
904
905
906void
907TimingSimpleCPU::printAddr(Addr a)
908{
909 dcachePort.printAddr(a);
910}
911
912
913////////////////////////////////////////////////////////////////////////
914//
915// TimingSimpleCPU Simulation Object
916//
917TimingSimpleCPU *
918TimingSimpleCPUParams::create()
919{
920 numThreads = 1;
921 if (!FullSystem && workload.size() != 1)
922 panic("only one workload allowed");
923 return new TimingSimpleCPU(this);
924}
|