132 return 1;
133 }
134}
135
136void
137TimingSimpleCPU::resume()
138{
139 DPRINTF(SimpleCPU, "Resume\n");
140 if (_status != SwitchedOut && _status != Idle) {
141 assert(system->getMemoryMode() == Enums::timing);
142
143 if (fetchEvent.scheduled())
144 deschedule(fetchEvent);
145
146 schedule(fetchEvent, nextCycle());
147 }
148
149 changeState(SimObject::Running);
150}
151
152void
153TimingSimpleCPU::switchOut()
154{
155 assert(_status == Running || _status == Idle);
156 _status = SwitchedOut;
157 numCycles += tickToCycles(curTick() - previousTick);
158
159 // If we've been scheduled to resume but are then told to switch out,
160 // we'll need to cancel it.
161 if (fetchEvent.scheduled())
162 deschedule(fetchEvent);
163}
164
165
166void
167TimingSimpleCPU::takeOverFrom(BaseCPU *oldCPU)
168{
169 BaseCPU::takeOverFrom(oldCPU);
170
171 // if any of this CPU's ThreadContexts are active, mark the CPU as
172 // running and schedule its tick event.
173 for (int i = 0; i < threadContexts.size(); ++i) {
174 ThreadContext *tc = threadContexts[i];
175 if (tc->status() == ThreadContext::Active && _status != Running) {
176 _status = Running;
177 break;
178 }
179 }
180
181 if (_status != Running) {
182 _status = Idle;
183 }
184 assert(threadContexts.size() == 1);
185 previousTick = curTick();
186}
187
188
189void
190TimingSimpleCPU::activateContext(ThreadID thread_num, int delay)
191{
192 DPRINTF(SimpleCPU, "ActivateContext %d (%d cycles)\n", thread_num, delay);
193
194 assert(thread_num == 0);
195 assert(thread);
196
197 assert(_status == Idle);
198
199 notIdleFraction++;
200 _status = Running;
201
202 // kick things off by initiating the fetch of the next instruction
203 schedule(fetchEvent, nextCycle(curTick() + ticks(delay)));
204}
205
206
207void
208TimingSimpleCPU::suspendContext(ThreadID thread_num)
209{
210 DPRINTF(SimpleCPU, "SuspendContext %d\n", thread_num);
211
212 assert(thread_num == 0);
213 assert(thread);
214
215 if (_status == Idle)
216 return;
217
218 assert(_status == Running);
219
220 // just change status to Idle... if status != Running,
221 // completeInst() will not initiate fetch of next instruction.
222
223 notIdleFraction--;
224 _status = Idle;
225}
226
227bool
228TimingSimpleCPU::handleReadPacket(PacketPtr pkt)
229{
230 RequestPtr req = pkt->req;
231 if (req->isMmappedIpr()) {
232 Tick delay;
233 delay = TheISA::handleIprRead(thread->getTC(), pkt);
234 new IprEvent(pkt, this, nextCycle(curTick() + delay));
235 _status = DcacheWaitResponse;
236 dcache_pkt = NULL;
237 } else if (!dcachePort.sendTimingReq(pkt)) {
238 _status = DcacheRetry;
239 dcache_pkt = pkt;
240 } else {
241 _status = DcacheWaitResponse;
242 // memory system takes ownership of packet
243 dcache_pkt = NULL;
244 }
245 return dcache_pkt == NULL;
246}
247
248void
249TimingSimpleCPU::sendData(RequestPtr req, uint8_t *data, uint64_t *res,
250 bool read)
251{
252 PacketPtr pkt;
253 buildPacket(pkt, req, read);
254 pkt->dataDynamicArray<uint8_t>(data);
255 if (req->getFlags().isSet(Request::NO_ACCESS)) {
256 assert(!dcache_pkt);
257 pkt->makeResponse();
258 completeDataAccess(pkt);
259 } else if (read) {
260 handleReadPacket(pkt);
261 } else {
262 bool do_access = true; // flag to suppress cache access
263
264 if (req->isLLSC()) {
265 do_access = TheISA::handleLockedWrite(thread, req);
266 } else if (req->isCondSwap()) {
267 assert(res);
268 req->setExtraData(*res);
269 }
270
271 if (do_access) {
272 dcache_pkt = pkt;
273 handleWritePacket();
274 } else {
275 _status = DcacheWaitResponse;
276 completeDataAccess(pkt);
277 }
278 }
279}
280
281void
282TimingSimpleCPU::sendSplitData(RequestPtr req1, RequestPtr req2,
283 RequestPtr req, uint8_t *data, bool read)
284{
285 PacketPtr pkt1, pkt2;
286 buildSplitPacket(pkt1, pkt2, req1, req2, req, data, read);
287 if (req->getFlags().isSet(Request::NO_ACCESS)) {
288 assert(!dcache_pkt);
289 pkt1->makeResponse();
290 completeDataAccess(pkt1);
291 } else if (read) {
292 SplitFragmentSenderState * send_state =
293 dynamic_cast<SplitFragmentSenderState *>(pkt1->senderState);
294 if (handleReadPacket(pkt1)) {
295 send_state->clearFromParent();
296 send_state = dynamic_cast<SplitFragmentSenderState *>(
297 pkt2->senderState);
298 if (handleReadPacket(pkt2)) {
299 send_state->clearFromParent();
300 }
301 }
302 } else {
303 dcache_pkt = pkt1;
304 SplitFragmentSenderState * send_state =
305 dynamic_cast<SplitFragmentSenderState *>(pkt1->senderState);
306 if (handleWritePacket()) {
307 send_state->clearFromParent();
308 dcache_pkt = pkt2;
309 send_state = dynamic_cast<SplitFragmentSenderState *>(
310 pkt2->senderState);
311 if (handleWritePacket()) {
312 send_state->clearFromParent();
313 }
314 }
315 }
316}
317
318void
319TimingSimpleCPU::translationFault(Fault fault)
320{
321 // fault may be NoFault in cases where a fault is suppressed,
322 // for instance prefetches.
323 numCycles += tickToCycles(curTick() - previousTick);
324 previousTick = curTick();
325
326 if (traceData) {
327 // Since there was a fault, we shouldn't trace this instruction.
328 delete traceData;
329 traceData = NULL;
330 }
331
332 postExecute();
333
334 if (getState() == SimObject::Draining) {
335 advancePC(fault);
336 completeDrain();
337 } else {
338 advanceInst(fault);
339 }
340}
341
342void
343TimingSimpleCPU::buildPacket(PacketPtr &pkt, RequestPtr req, bool read)
344{
345 MemCmd cmd;
346 if (read) {
347 cmd = MemCmd::ReadReq;
348 if (req->isLLSC())
349 cmd = MemCmd::LoadLockedReq;
350 } else {
351 cmd = MemCmd::WriteReq;
352 if (req->isLLSC()) {
353 cmd = MemCmd::StoreCondReq;
354 } else if (req->isSwap()) {
355 cmd = MemCmd::SwapReq;
356 }
357 }
358 pkt = new Packet(req, cmd);
359}
360
361void
362TimingSimpleCPU::buildSplitPacket(PacketPtr &pkt1, PacketPtr &pkt2,
363 RequestPtr req1, RequestPtr req2, RequestPtr req,
364 uint8_t *data, bool read)
365{
366 pkt1 = pkt2 = NULL;
367
368 assert(!req1->isMmappedIpr() && !req2->isMmappedIpr());
369
370 if (req->getFlags().isSet(Request::NO_ACCESS)) {
371 buildPacket(pkt1, req, read);
372 return;
373 }
374
375 buildPacket(pkt1, req1, read);
376 buildPacket(pkt2, req2, read);
377
378 req->setPhys(req1->getPaddr(), req->getSize(), req1->getFlags(), dataMasterId());
379 PacketPtr pkt = new Packet(req, pkt1->cmd.responseCommand());
380
381 pkt->dataDynamicArray<uint8_t>(data);
382 pkt1->dataStatic<uint8_t>(data);
383 pkt2->dataStatic<uint8_t>(data + req1->getSize());
384
385 SplitMainSenderState * main_send_state = new SplitMainSenderState;
386 pkt->senderState = main_send_state;
387 main_send_state->fragments[0] = pkt1;
388 main_send_state->fragments[1] = pkt2;
389 main_send_state->outstanding = 2;
390 pkt1->senderState = new SplitFragmentSenderState(pkt, 0);
391 pkt2->senderState = new SplitFragmentSenderState(pkt, 1);
392}
393
394Fault
395TimingSimpleCPU::readMem(Addr addr, uint8_t *data,
396 unsigned size, unsigned flags)
397{
398 Fault fault;
399 const int asid = 0;
400 const ThreadID tid = 0;
401 const Addr pc = thread->instAddr();
402 unsigned block_size = dcachePort.peerBlockSize();
403 BaseTLB::Mode mode = BaseTLB::Read;
404
405 if (traceData) {
406 traceData->setAddr(addr);
407 }
408
409 RequestPtr req = new Request(asid, addr, size,
410 flags, dataMasterId(), pc, _cpuId, tid);
411
412 Addr split_addr = roundDown(addr + size - 1, block_size);
413 assert(split_addr <= addr || split_addr - addr < block_size);
414
415 _status = DTBWaitResponse;
416 if (split_addr > addr) {
417 RequestPtr req1, req2;
418 assert(!req->isLLSC() && !req->isSwap());
419 req->splitOnVaddr(split_addr, req1, req2);
420
421 WholeTranslationState *state =
422 new WholeTranslationState(req, req1, req2, new uint8_t[size],
423 NULL, mode);
424 DataTranslation<TimingSimpleCPU *> *trans1 =
425 new DataTranslation<TimingSimpleCPU *>(this, state, 0);
426 DataTranslation<TimingSimpleCPU *> *trans2 =
427 new DataTranslation<TimingSimpleCPU *>(this, state, 1);
428
429 thread->dtb->translateTiming(req1, tc, trans1, mode);
430 thread->dtb->translateTiming(req2, tc, trans2, mode);
431 } else {
432 WholeTranslationState *state =
433 new WholeTranslationState(req, new uint8_t[size], NULL, mode);
434 DataTranslation<TimingSimpleCPU *> *translation
435 = new DataTranslation<TimingSimpleCPU *>(this, state);
436 thread->dtb->translateTiming(req, tc, translation, mode);
437 }
438
439 return NoFault;
440}
441
442bool
443TimingSimpleCPU::handleWritePacket()
444{
445 RequestPtr req = dcache_pkt->req;
446 if (req->isMmappedIpr()) {
447 Tick delay;
448 delay = TheISA::handleIprWrite(thread->getTC(), dcache_pkt);
449 new IprEvent(dcache_pkt, this, nextCycle(curTick() + delay));
450 _status = DcacheWaitResponse;
451 dcache_pkt = NULL;
452 } else if (!dcachePort.sendTimingReq(dcache_pkt)) {
453 _status = DcacheRetry;
454 } else {
455 _status = DcacheWaitResponse;
456 // memory system takes ownership of packet
457 dcache_pkt = NULL;
458 }
459 return dcache_pkt == NULL;
460}
461
462Fault
463TimingSimpleCPU::writeMem(uint8_t *data, unsigned size,
464 Addr addr, unsigned flags, uint64_t *res)
465{
466 uint8_t *newData = new uint8_t[size];
467 memcpy(newData, data, size);
468
469 const int asid = 0;
470 const ThreadID tid = 0;
471 const Addr pc = thread->instAddr();
472 unsigned block_size = dcachePort.peerBlockSize();
473 BaseTLB::Mode mode = BaseTLB::Write;
474
475 if (traceData) {
476 traceData->setAddr(addr);
477 }
478
479 RequestPtr req = new Request(asid, addr, size,
480 flags, dataMasterId(), pc, _cpuId, tid);
481
482 Addr split_addr = roundDown(addr + size - 1, block_size);
483 assert(split_addr <= addr || split_addr - addr < block_size);
484
485 _status = DTBWaitResponse;
486 if (split_addr > addr) {
487 RequestPtr req1, req2;
488 assert(!req->isLLSC() && !req->isSwap());
489 req->splitOnVaddr(split_addr, req1, req2);
490
491 WholeTranslationState *state =
492 new WholeTranslationState(req, req1, req2, newData, res, mode);
493 DataTranslation<TimingSimpleCPU *> *trans1 =
494 new DataTranslation<TimingSimpleCPU *>(this, state, 0);
495 DataTranslation<TimingSimpleCPU *> *trans2 =
496 new DataTranslation<TimingSimpleCPU *>(this, state, 1);
497
498 thread->dtb->translateTiming(req1, tc, trans1, mode);
499 thread->dtb->translateTiming(req2, tc, trans2, mode);
500 } else {
501 WholeTranslationState *state =
502 new WholeTranslationState(req, newData, res, mode);
503 DataTranslation<TimingSimpleCPU *> *translation =
504 new DataTranslation<TimingSimpleCPU *>(this, state);
505 thread->dtb->translateTiming(req, tc, translation, mode);
506 }
507
508 // Translation faults will be returned via finishTranslation()
509 return NoFault;
510}
511
512
513void
514TimingSimpleCPU::finishTranslation(WholeTranslationState *state)
515{
516 _status = Running;
517
518 if (state->getFault() != NoFault) {
519 if (state->isPrefetch()) {
520 state->setNoFault();
521 }
522 delete [] state->data;
523 state->deleteReqs();
524 translationFault(state->getFault());
525 } else {
526 if (!state->isSplit) {
527 sendData(state->mainReq, state->data, state->res,
528 state->mode == BaseTLB::Read);
529 } else {
530 sendSplitData(state->sreqLow, state->sreqHigh, state->mainReq,
531 state->data, state->mode == BaseTLB::Read);
532 }
533 }
534
535 delete state;
536}
537
538
539void
540TimingSimpleCPU::fetch()
541{
542 DPRINTF(SimpleCPU, "Fetch\n");
543
544 if (!curStaticInst || !curStaticInst->isDelayedCommit())
545 checkForInterrupts();
546
547 checkPcEventQueue();
548
549 // We must have just got suspended by a PC event
550 if (_status == Idle)
551 return;
552
553 TheISA::PCState pcState = thread->pcState();
554 bool needToFetch = !isRomMicroPC(pcState.microPC()) && !curMacroStaticInst;
555
556 if (needToFetch) {
557 _status = Running;
558 Request *ifetch_req = new Request();
559 ifetch_req->setThreadContext(_cpuId, /* thread ID */ 0);
560 setupFetchRequest(ifetch_req);
561 DPRINTF(SimpleCPU, "Translating address %#x\n", ifetch_req->getVaddr());
562 thread->itb->translateTiming(ifetch_req, tc, &fetchTranslation,
563 BaseTLB::Execute);
564 } else {
565 _status = IcacheWaitResponse;
566 completeIfetch(NULL);
567
568 numCycles += tickToCycles(curTick() - previousTick);
569 previousTick = curTick();
570 }
571}
572
573
574void
575TimingSimpleCPU::sendFetch(Fault fault, RequestPtr req, ThreadContext *tc)
576{
577 if (fault == NoFault) {
578 DPRINTF(SimpleCPU, "Sending fetch for addr %#x(pa: %#x)\n",
579 req->getVaddr(), req->getPaddr());
580 ifetch_pkt = new Packet(req, MemCmd::ReadReq);
581 ifetch_pkt->dataStatic(&inst);
582 DPRINTF(SimpleCPU, " -- pkt addr: %#x\n", ifetch_pkt->getAddr());
583
584 if (!icachePort.sendTimingReq(ifetch_pkt)) {
585 // Need to wait for retry
586 _status = IcacheRetry;
587 } else {
588 // Need to wait for cache to respond
589 _status = IcacheWaitResponse;
590 // ownership of packet transferred to memory system
591 ifetch_pkt = NULL;
592 }
593 } else {
594 DPRINTF(SimpleCPU, "Translation of addr %#x faulted\n", req->getVaddr());
595 delete req;
596 // fetch fault: advance directly to next instruction (fault handler)
597 _status = Running;
598 advanceInst(fault);
599 }
600
601 numCycles += tickToCycles(curTick() - previousTick);
602 previousTick = curTick();
603}
604
605
606void
607TimingSimpleCPU::advanceInst(Fault fault)
608{
609
610 if (_status == Faulting)
611 return;
612
613 if (fault != NoFault) {
614 advancePC(fault);
615 DPRINTF(SimpleCPU, "Fault occured, scheduling fetch event\n");
616 reschedule(fetchEvent, nextCycle(), true);
617 _status = Faulting;
618 return;
619 }
620
621
622 if (!stayAtPC)
623 advancePC(fault);
624
625 if (_status == Running) {
626 // kick off fetch of next instruction... callback from icache
627 // response will cause that instruction to be executed,
628 // keeping the CPU running.
629 fetch();
630 }
631}
632
633
634void
635TimingSimpleCPU::completeIfetch(PacketPtr pkt)
636{
637 DPRINTF(SimpleCPU, "Complete ICache Fetch for addr %#x\n", pkt ?
638 pkt->getAddr() : 0);
639
640 // received a response from the icache: execute the received
641 // instruction
642
643 assert(!pkt || !pkt->isError());
644 assert(_status == IcacheWaitResponse);
645
646 _status = Running;
647
648 numCycles += tickToCycles(curTick() - previousTick);
649 previousTick = curTick();
650
651 if (getState() == SimObject::Draining) {
652 if (pkt) {
653 delete pkt->req;
654 delete pkt;
655 }
656
657 completeDrain();
658 return;
659 }
660
661 preExecute();
662 if (curStaticInst && curStaticInst->isMemRef()) {
663 // load or store: just send to dcache
664 Fault fault = curStaticInst->initiateAcc(this, traceData);
665
666 // If we're not running now the instruction will complete in a dcache
667 // response callback or the instruction faulted and has started an
668 // ifetch
669 if (_status == Running) {
670 if (fault != NoFault && traceData) {
671 // If there was a fault, we shouldn't trace this instruction.
672 delete traceData;
673 traceData = NULL;
674 }
675
676 postExecute();
677 // @todo remove me after debugging with legion done
678 if (curStaticInst && (!curStaticInst->isMicroop() ||
679 curStaticInst->isFirstMicroop()))
680 instCnt++;
681 advanceInst(fault);
682 }
683 } else if (curStaticInst) {
684 // non-memory instruction: execute completely now
685 Fault fault = curStaticInst->execute(this, traceData);
686
687 // keep an instruction count
688 if (fault == NoFault)
689 countInst();
690 else if (traceData && !DTRACE(ExecFaulting)) {
691 delete traceData;
692 traceData = NULL;
693 }
694
695 postExecute();
696 // @todo remove me after debugging with legion done
697 if (curStaticInst && (!curStaticInst->isMicroop() ||
698 curStaticInst->isFirstMicroop()))
699 instCnt++;
700 advanceInst(fault);
701 } else {
702 advanceInst(NoFault);
703 }
704
705 if (pkt) {
706 delete pkt->req;
707 delete pkt;
708 }
709}
710
711void
712TimingSimpleCPU::IcachePort::ITickEvent::process()
713{
714 cpu->completeIfetch(pkt);
715}
716
717bool
718TimingSimpleCPU::IcachePort::recvTimingResp(PacketPtr pkt)
719{
720 if (!pkt->wasNacked()) {
721 DPRINTF(SimpleCPU, "Received timing response %#x\n", pkt->getAddr());
722 // delay processing of returned data until next CPU clock edge
723 Tick next_tick = cpu->nextCycle(curTick());
724
725 if (next_tick == curTick())
726 cpu->completeIfetch(pkt);
727 else
728 tickEvent.schedule(pkt, next_tick);
729
730 return true;
731 } else {
732 assert(cpu->_status == IcacheWaitResponse);
733 pkt->reinitNacked();
734 if (!sendTimingReq(pkt)) {
735 cpu->_status = IcacheRetry;
736 cpu->ifetch_pkt = pkt;
737 }
738 }
739
740 return true;
741}
742
743void
744TimingSimpleCPU::IcachePort::recvRetry()
745{
746 // we shouldn't get a retry unless we have a packet that we're
747 // waiting to transmit
748 assert(cpu->ifetch_pkt != NULL);
749 assert(cpu->_status == IcacheRetry);
750 PacketPtr tmp = cpu->ifetch_pkt;
751 if (sendTimingReq(tmp)) {
752 cpu->_status = IcacheWaitResponse;
753 cpu->ifetch_pkt = NULL;
754 }
755}
756
757void
758TimingSimpleCPU::completeDataAccess(PacketPtr pkt)
759{
760 // received a response from the dcache: complete the load or store
761 // instruction
762 assert(!pkt->isError());
763 assert(_status == DcacheWaitResponse || _status == DTBWaitResponse ||
764 pkt->req->getFlags().isSet(Request::NO_ACCESS));
765
766 numCycles += tickToCycles(curTick() - previousTick);
767 previousTick = curTick();
768
769 if (pkt->senderState) {
770 SplitFragmentSenderState * send_state =
771 dynamic_cast<SplitFragmentSenderState *>(pkt->senderState);
772 assert(send_state);
773 delete pkt->req;
774 delete pkt;
775 PacketPtr big_pkt = send_state->bigPkt;
776 delete send_state;
777
778 SplitMainSenderState * main_send_state =
779 dynamic_cast<SplitMainSenderState *>(big_pkt->senderState);
780 assert(main_send_state);
781 // Record the fact that this packet is no longer outstanding.
782 assert(main_send_state->outstanding != 0);
783 main_send_state->outstanding--;
784
785 if (main_send_state->outstanding) {
786 return;
787 } else {
788 delete main_send_state;
789 big_pkt->senderState = NULL;
790 pkt = big_pkt;
791 }
792 }
793
794 _status = Running;
795
796 Fault fault = curStaticInst->completeAcc(pkt, this, traceData);
797
798 // keep an instruction count
799 if (fault == NoFault)
800 countInst();
801 else if (traceData) {
802 // If there was a fault, we shouldn't trace this instruction.
803 delete traceData;
804 traceData = NULL;
805 }
806
807 // the locked flag may be cleared on the response packet, so check
808 // pkt->req and not pkt to see if it was a load-locked
809 if (pkt->isRead() && pkt->req->isLLSC()) {
810 TheISA::handleLockedRead(thread, pkt->req);
811 }
812
813 delete pkt->req;
814 delete pkt;
815
816 postExecute();
817
818 if (getState() == SimObject::Draining) {
819 advancePC(fault);
820 completeDrain();
821
822 return;
823 }
824
825 advanceInst(fault);
826}
827
828
829void
830TimingSimpleCPU::completeDrain()
831{
| 134 return 1;
135 }
136}
137
138void
139TimingSimpleCPU::resume()
140{
141 DPRINTF(SimpleCPU, "Resume\n");
142 if (_status != SwitchedOut && _status != Idle) {
143 assert(system->getMemoryMode() == Enums::timing);
144
145 if (fetchEvent.scheduled())
146 deschedule(fetchEvent);
147
148 schedule(fetchEvent, nextCycle());
149 }
150
151 changeState(SimObject::Running);
152}
153
154void
155TimingSimpleCPU::switchOut()
156{
157 assert(_status == Running || _status == Idle);
158 _status = SwitchedOut;
159 numCycles += tickToCycles(curTick() - previousTick);
160
161 // If we've been scheduled to resume but are then told to switch out,
162 // we'll need to cancel it.
163 if (fetchEvent.scheduled())
164 deschedule(fetchEvent);
165}
166
167
168void
169TimingSimpleCPU::takeOverFrom(BaseCPU *oldCPU)
170{
171 BaseCPU::takeOverFrom(oldCPU);
172
173 // if any of this CPU's ThreadContexts are active, mark the CPU as
174 // running and schedule its tick event.
175 for (int i = 0; i < threadContexts.size(); ++i) {
176 ThreadContext *tc = threadContexts[i];
177 if (tc->status() == ThreadContext::Active && _status != Running) {
178 _status = Running;
179 break;
180 }
181 }
182
183 if (_status != Running) {
184 _status = Idle;
185 }
186 assert(threadContexts.size() == 1);
187 previousTick = curTick();
188}
189
190
191void
192TimingSimpleCPU::activateContext(ThreadID thread_num, int delay)
193{
194 DPRINTF(SimpleCPU, "ActivateContext %d (%d cycles)\n", thread_num, delay);
195
196 assert(thread_num == 0);
197 assert(thread);
198
199 assert(_status == Idle);
200
201 notIdleFraction++;
202 _status = Running;
203
204 // kick things off by initiating the fetch of the next instruction
205 schedule(fetchEvent, nextCycle(curTick() + ticks(delay)));
206}
207
208
209void
210TimingSimpleCPU::suspendContext(ThreadID thread_num)
211{
212 DPRINTF(SimpleCPU, "SuspendContext %d\n", thread_num);
213
214 assert(thread_num == 0);
215 assert(thread);
216
217 if (_status == Idle)
218 return;
219
220 assert(_status == Running);
221
222 // just change status to Idle... if status != Running,
223 // completeInst() will not initiate fetch of next instruction.
224
225 notIdleFraction--;
226 _status = Idle;
227}
228
229bool
230TimingSimpleCPU::handleReadPacket(PacketPtr pkt)
231{
232 RequestPtr req = pkt->req;
233 if (req->isMmappedIpr()) {
234 Tick delay;
235 delay = TheISA::handleIprRead(thread->getTC(), pkt);
236 new IprEvent(pkt, this, nextCycle(curTick() + delay));
237 _status = DcacheWaitResponse;
238 dcache_pkt = NULL;
239 } else if (!dcachePort.sendTimingReq(pkt)) {
240 _status = DcacheRetry;
241 dcache_pkt = pkt;
242 } else {
243 _status = DcacheWaitResponse;
244 // memory system takes ownership of packet
245 dcache_pkt = NULL;
246 }
247 return dcache_pkt == NULL;
248}
249
250void
251TimingSimpleCPU::sendData(RequestPtr req, uint8_t *data, uint64_t *res,
252 bool read)
253{
254 PacketPtr pkt;
255 buildPacket(pkt, req, read);
256 pkt->dataDynamicArray<uint8_t>(data);
257 if (req->getFlags().isSet(Request::NO_ACCESS)) {
258 assert(!dcache_pkt);
259 pkt->makeResponse();
260 completeDataAccess(pkt);
261 } else if (read) {
262 handleReadPacket(pkt);
263 } else {
264 bool do_access = true; // flag to suppress cache access
265
266 if (req->isLLSC()) {
267 do_access = TheISA::handleLockedWrite(thread, req);
268 } else if (req->isCondSwap()) {
269 assert(res);
270 req->setExtraData(*res);
271 }
272
273 if (do_access) {
274 dcache_pkt = pkt;
275 handleWritePacket();
276 } else {
277 _status = DcacheWaitResponse;
278 completeDataAccess(pkt);
279 }
280 }
281}
282
283void
284TimingSimpleCPU::sendSplitData(RequestPtr req1, RequestPtr req2,
285 RequestPtr req, uint8_t *data, bool read)
286{
287 PacketPtr pkt1, pkt2;
288 buildSplitPacket(pkt1, pkt2, req1, req2, req, data, read);
289 if (req->getFlags().isSet(Request::NO_ACCESS)) {
290 assert(!dcache_pkt);
291 pkt1->makeResponse();
292 completeDataAccess(pkt1);
293 } else if (read) {
294 SplitFragmentSenderState * send_state =
295 dynamic_cast<SplitFragmentSenderState *>(pkt1->senderState);
296 if (handleReadPacket(pkt1)) {
297 send_state->clearFromParent();
298 send_state = dynamic_cast<SplitFragmentSenderState *>(
299 pkt2->senderState);
300 if (handleReadPacket(pkt2)) {
301 send_state->clearFromParent();
302 }
303 }
304 } else {
305 dcache_pkt = pkt1;
306 SplitFragmentSenderState * send_state =
307 dynamic_cast<SplitFragmentSenderState *>(pkt1->senderState);
308 if (handleWritePacket()) {
309 send_state->clearFromParent();
310 dcache_pkt = pkt2;
311 send_state = dynamic_cast<SplitFragmentSenderState *>(
312 pkt2->senderState);
313 if (handleWritePacket()) {
314 send_state->clearFromParent();
315 }
316 }
317 }
318}
319
320void
321TimingSimpleCPU::translationFault(Fault fault)
322{
323 // fault may be NoFault in cases where a fault is suppressed,
324 // for instance prefetches.
325 numCycles += tickToCycles(curTick() - previousTick);
326 previousTick = curTick();
327
328 if (traceData) {
329 // Since there was a fault, we shouldn't trace this instruction.
330 delete traceData;
331 traceData = NULL;
332 }
333
334 postExecute();
335
336 if (getState() == SimObject::Draining) {
337 advancePC(fault);
338 completeDrain();
339 } else {
340 advanceInst(fault);
341 }
342}
343
344void
345TimingSimpleCPU::buildPacket(PacketPtr &pkt, RequestPtr req, bool read)
346{
347 MemCmd cmd;
348 if (read) {
349 cmd = MemCmd::ReadReq;
350 if (req->isLLSC())
351 cmd = MemCmd::LoadLockedReq;
352 } else {
353 cmd = MemCmd::WriteReq;
354 if (req->isLLSC()) {
355 cmd = MemCmd::StoreCondReq;
356 } else if (req->isSwap()) {
357 cmd = MemCmd::SwapReq;
358 }
359 }
360 pkt = new Packet(req, cmd);
361}
362
363void
364TimingSimpleCPU::buildSplitPacket(PacketPtr &pkt1, PacketPtr &pkt2,
365 RequestPtr req1, RequestPtr req2, RequestPtr req,
366 uint8_t *data, bool read)
367{
368 pkt1 = pkt2 = NULL;
369
370 assert(!req1->isMmappedIpr() && !req2->isMmappedIpr());
371
372 if (req->getFlags().isSet(Request::NO_ACCESS)) {
373 buildPacket(pkt1, req, read);
374 return;
375 }
376
377 buildPacket(pkt1, req1, read);
378 buildPacket(pkt2, req2, read);
379
380 req->setPhys(req1->getPaddr(), req->getSize(), req1->getFlags(), dataMasterId());
381 PacketPtr pkt = new Packet(req, pkt1->cmd.responseCommand());
382
383 pkt->dataDynamicArray<uint8_t>(data);
384 pkt1->dataStatic<uint8_t>(data);
385 pkt2->dataStatic<uint8_t>(data + req1->getSize());
386
387 SplitMainSenderState * main_send_state = new SplitMainSenderState;
388 pkt->senderState = main_send_state;
389 main_send_state->fragments[0] = pkt1;
390 main_send_state->fragments[1] = pkt2;
391 main_send_state->outstanding = 2;
392 pkt1->senderState = new SplitFragmentSenderState(pkt, 0);
393 pkt2->senderState = new SplitFragmentSenderState(pkt, 1);
394}
395
396Fault
397TimingSimpleCPU::readMem(Addr addr, uint8_t *data,
398 unsigned size, unsigned flags)
399{
400 Fault fault;
401 const int asid = 0;
402 const ThreadID tid = 0;
403 const Addr pc = thread->instAddr();
404 unsigned block_size = dcachePort.peerBlockSize();
405 BaseTLB::Mode mode = BaseTLB::Read;
406
407 if (traceData) {
408 traceData->setAddr(addr);
409 }
410
411 RequestPtr req = new Request(asid, addr, size,
412 flags, dataMasterId(), pc, _cpuId, tid);
413
414 Addr split_addr = roundDown(addr + size - 1, block_size);
415 assert(split_addr <= addr || split_addr - addr < block_size);
416
417 _status = DTBWaitResponse;
418 if (split_addr > addr) {
419 RequestPtr req1, req2;
420 assert(!req->isLLSC() && !req->isSwap());
421 req->splitOnVaddr(split_addr, req1, req2);
422
423 WholeTranslationState *state =
424 new WholeTranslationState(req, req1, req2, new uint8_t[size],
425 NULL, mode);
426 DataTranslation<TimingSimpleCPU *> *trans1 =
427 new DataTranslation<TimingSimpleCPU *>(this, state, 0);
428 DataTranslation<TimingSimpleCPU *> *trans2 =
429 new DataTranslation<TimingSimpleCPU *>(this, state, 1);
430
431 thread->dtb->translateTiming(req1, tc, trans1, mode);
432 thread->dtb->translateTiming(req2, tc, trans2, mode);
433 } else {
434 WholeTranslationState *state =
435 new WholeTranslationState(req, new uint8_t[size], NULL, mode);
436 DataTranslation<TimingSimpleCPU *> *translation
437 = new DataTranslation<TimingSimpleCPU *>(this, state);
438 thread->dtb->translateTiming(req, tc, translation, mode);
439 }
440
441 return NoFault;
442}
443
444bool
445TimingSimpleCPU::handleWritePacket()
446{
447 RequestPtr req = dcache_pkt->req;
448 if (req->isMmappedIpr()) {
449 Tick delay;
450 delay = TheISA::handleIprWrite(thread->getTC(), dcache_pkt);
451 new IprEvent(dcache_pkt, this, nextCycle(curTick() + delay));
452 _status = DcacheWaitResponse;
453 dcache_pkt = NULL;
454 } else if (!dcachePort.sendTimingReq(dcache_pkt)) {
455 _status = DcacheRetry;
456 } else {
457 _status = DcacheWaitResponse;
458 // memory system takes ownership of packet
459 dcache_pkt = NULL;
460 }
461 return dcache_pkt == NULL;
462}
463
464Fault
465TimingSimpleCPU::writeMem(uint8_t *data, unsigned size,
466 Addr addr, unsigned flags, uint64_t *res)
467{
468 uint8_t *newData = new uint8_t[size];
469 memcpy(newData, data, size);
470
471 const int asid = 0;
472 const ThreadID tid = 0;
473 const Addr pc = thread->instAddr();
474 unsigned block_size = dcachePort.peerBlockSize();
475 BaseTLB::Mode mode = BaseTLB::Write;
476
477 if (traceData) {
478 traceData->setAddr(addr);
479 }
480
481 RequestPtr req = new Request(asid, addr, size,
482 flags, dataMasterId(), pc, _cpuId, tid);
483
484 Addr split_addr = roundDown(addr + size - 1, block_size);
485 assert(split_addr <= addr || split_addr - addr < block_size);
486
487 _status = DTBWaitResponse;
488 if (split_addr > addr) {
489 RequestPtr req1, req2;
490 assert(!req->isLLSC() && !req->isSwap());
491 req->splitOnVaddr(split_addr, req1, req2);
492
493 WholeTranslationState *state =
494 new WholeTranslationState(req, req1, req2, newData, res, mode);
495 DataTranslation<TimingSimpleCPU *> *trans1 =
496 new DataTranslation<TimingSimpleCPU *>(this, state, 0);
497 DataTranslation<TimingSimpleCPU *> *trans2 =
498 new DataTranslation<TimingSimpleCPU *>(this, state, 1);
499
500 thread->dtb->translateTiming(req1, tc, trans1, mode);
501 thread->dtb->translateTiming(req2, tc, trans2, mode);
502 } else {
503 WholeTranslationState *state =
504 new WholeTranslationState(req, newData, res, mode);
505 DataTranslation<TimingSimpleCPU *> *translation =
506 new DataTranslation<TimingSimpleCPU *>(this, state);
507 thread->dtb->translateTiming(req, tc, translation, mode);
508 }
509
510 // Translation faults will be returned via finishTranslation()
511 return NoFault;
512}
513
514
515void
516TimingSimpleCPU::finishTranslation(WholeTranslationState *state)
517{
518 _status = Running;
519
520 if (state->getFault() != NoFault) {
521 if (state->isPrefetch()) {
522 state->setNoFault();
523 }
524 delete [] state->data;
525 state->deleteReqs();
526 translationFault(state->getFault());
527 } else {
528 if (!state->isSplit) {
529 sendData(state->mainReq, state->data, state->res,
530 state->mode == BaseTLB::Read);
531 } else {
532 sendSplitData(state->sreqLow, state->sreqHigh, state->mainReq,
533 state->data, state->mode == BaseTLB::Read);
534 }
535 }
536
537 delete state;
538}
539
540
541void
542TimingSimpleCPU::fetch()
543{
544 DPRINTF(SimpleCPU, "Fetch\n");
545
546 if (!curStaticInst || !curStaticInst->isDelayedCommit())
547 checkForInterrupts();
548
549 checkPcEventQueue();
550
551 // We must have just got suspended by a PC event
552 if (_status == Idle)
553 return;
554
555 TheISA::PCState pcState = thread->pcState();
556 bool needToFetch = !isRomMicroPC(pcState.microPC()) && !curMacroStaticInst;
557
558 if (needToFetch) {
559 _status = Running;
560 Request *ifetch_req = new Request();
561 ifetch_req->setThreadContext(_cpuId, /* thread ID */ 0);
562 setupFetchRequest(ifetch_req);
563 DPRINTF(SimpleCPU, "Translating address %#x\n", ifetch_req->getVaddr());
564 thread->itb->translateTiming(ifetch_req, tc, &fetchTranslation,
565 BaseTLB::Execute);
566 } else {
567 _status = IcacheWaitResponse;
568 completeIfetch(NULL);
569
570 numCycles += tickToCycles(curTick() - previousTick);
571 previousTick = curTick();
572 }
573}
574
575
576void
577TimingSimpleCPU::sendFetch(Fault fault, RequestPtr req, ThreadContext *tc)
578{
579 if (fault == NoFault) {
580 DPRINTF(SimpleCPU, "Sending fetch for addr %#x(pa: %#x)\n",
581 req->getVaddr(), req->getPaddr());
582 ifetch_pkt = new Packet(req, MemCmd::ReadReq);
583 ifetch_pkt->dataStatic(&inst);
584 DPRINTF(SimpleCPU, " -- pkt addr: %#x\n", ifetch_pkt->getAddr());
585
586 if (!icachePort.sendTimingReq(ifetch_pkt)) {
587 // Need to wait for retry
588 _status = IcacheRetry;
589 } else {
590 // Need to wait for cache to respond
591 _status = IcacheWaitResponse;
592 // ownership of packet transferred to memory system
593 ifetch_pkt = NULL;
594 }
595 } else {
596 DPRINTF(SimpleCPU, "Translation of addr %#x faulted\n", req->getVaddr());
597 delete req;
598 // fetch fault: advance directly to next instruction (fault handler)
599 _status = Running;
600 advanceInst(fault);
601 }
602
603 numCycles += tickToCycles(curTick() - previousTick);
604 previousTick = curTick();
605}
606
607
608void
609TimingSimpleCPU::advanceInst(Fault fault)
610{
611
612 if (_status == Faulting)
613 return;
614
615 if (fault != NoFault) {
616 advancePC(fault);
617 DPRINTF(SimpleCPU, "Fault occured, scheduling fetch event\n");
618 reschedule(fetchEvent, nextCycle(), true);
619 _status = Faulting;
620 return;
621 }
622
623
624 if (!stayAtPC)
625 advancePC(fault);
626
627 if (_status == Running) {
628 // kick off fetch of next instruction... callback from icache
629 // response will cause that instruction to be executed,
630 // keeping the CPU running.
631 fetch();
632 }
633}
634
635
636void
637TimingSimpleCPU::completeIfetch(PacketPtr pkt)
638{
639 DPRINTF(SimpleCPU, "Complete ICache Fetch for addr %#x\n", pkt ?
640 pkt->getAddr() : 0);
641
642 // received a response from the icache: execute the received
643 // instruction
644
645 assert(!pkt || !pkt->isError());
646 assert(_status == IcacheWaitResponse);
647
648 _status = Running;
649
650 numCycles += tickToCycles(curTick() - previousTick);
651 previousTick = curTick();
652
653 if (getState() == SimObject::Draining) {
654 if (pkt) {
655 delete pkt->req;
656 delete pkt;
657 }
658
659 completeDrain();
660 return;
661 }
662
663 preExecute();
664 if (curStaticInst && curStaticInst->isMemRef()) {
665 // load or store: just send to dcache
666 Fault fault = curStaticInst->initiateAcc(this, traceData);
667
668 // If we're not running now the instruction will complete in a dcache
669 // response callback or the instruction faulted and has started an
670 // ifetch
671 if (_status == Running) {
672 if (fault != NoFault && traceData) {
673 // If there was a fault, we shouldn't trace this instruction.
674 delete traceData;
675 traceData = NULL;
676 }
677
678 postExecute();
679 // @todo remove me after debugging with legion done
680 if (curStaticInst && (!curStaticInst->isMicroop() ||
681 curStaticInst->isFirstMicroop()))
682 instCnt++;
683 advanceInst(fault);
684 }
685 } else if (curStaticInst) {
686 // non-memory instruction: execute completely now
687 Fault fault = curStaticInst->execute(this, traceData);
688
689 // keep an instruction count
690 if (fault == NoFault)
691 countInst();
692 else if (traceData && !DTRACE(ExecFaulting)) {
693 delete traceData;
694 traceData = NULL;
695 }
696
697 postExecute();
698 // @todo remove me after debugging with legion done
699 if (curStaticInst && (!curStaticInst->isMicroop() ||
700 curStaticInst->isFirstMicroop()))
701 instCnt++;
702 advanceInst(fault);
703 } else {
704 advanceInst(NoFault);
705 }
706
707 if (pkt) {
708 delete pkt->req;
709 delete pkt;
710 }
711}
712
713void
714TimingSimpleCPU::IcachePort::ITickEvent::process()
715{
716 cpu->completeIfetch(pkt);
717}
718
719bool
720TimingSimpleCPU::IcachePort::recvTimingResp(PacketPtr pkt)
721{
722 if (!pkt->wasNacked()) {
723 DPRINTF(SimpleCPU, "Received timing response %#x\n", pkt->getAddr());
724 // delay processing of returned data until next CPU clock edge
725 Tick next_tick = cpu->nextCycle(curTick());
726
727 if (next_tick == curTick())
728 cpu->completeIfetch(pkt);
729 else
730 tickEvent.schedule(pkt, next_tick);
731
732 return true;
733 } else {
734 assert(cpu->_status == IcacheWaitResponse);
735 pkt->reinitNacked();
736 if (!sendTimingReq(pkt)) {
737 cpu->_status = IcacheRetry;
738 cpu->ifetch_pkt = pkt;
739 }
740 }
741
742 return true;
743}
744
745void
746TimingSimpleCPU::IcachePort::recvRetry()
747{
748 // we shouldn't get a retry unless we have a packet that we're
749 // waiting to transmit
750 assert(cpu->ifetch_pkt != NULL);
751 assert(cpu->_status == IcacheRetry);
752 PacketPtr tmp = cpu->ifetch_pkt;
753 if (sendTimingReq(tmp)) {
754 cpu->_status = IcacheWaitResponse;
755 cpu->ifetch_pkt = NULL;
756 }
757}
758
759void
760TimingSimpleCPU::completeDataAccess(PacketPtr pkt)
761{
762 // received a response from the dcache: complete the load or store
763 // instruction
764 assert(!pkt->isError());
765 assert(_status == DcacheWaitResponse || _status == DTBWaitResponse ||
766 pkt->req->getFlags().isSet(Request::NO_ACCESS));
767
768 numCycles += tickToCycles(curTick() - previousTick);
769 previousTick = curTick();
770
771 if (pkt->senderState) {
772 SplitFragmentSenderState * send_state =
773 dynamic_cast<SplitFragmentSenderState *>(pkt->senderState);
774 assert(send_state);
775 delete pkt->req;
776 delete pkt;
777 PacketPtr big_pkt = send_state->bigPkt;
778 delete send_state;
779
780 SplitMainSenderState * main_send_state =
781 dynamic_cast<SplitMainSenderState *>(big_pkt->senderState);
782 assert(main_send_state);
783 // Record the fact that this packet is no longer outstanding.
784 assert(main_send_state->outstanding != 0);
785 main_send_state->outstanding--;
786
787 if (main_send_state->outstanding) {
788 return;
789 } else {
790 delete main_send_state;
791 big_pkt->senderState = NULL;
792 pkt = big_pkt;
793 }
794 }
795
796 _status = Running;
797
798 Fault fault = curStaticInst->completeAcc(pkt, this, traceData);
799
800 // keep an instruction count
801 if (fault == NoFault)
802 countInst();
803 else if (traceData) {
804 // If there was a fault, we shouldn't trace this instruction.
805 delete traceData;
806 traceData = NULL;
807 }
808
809 // the locked flag may be cleared on the response packet, so check
810 // pkt->req and not pkt to see if it was a load-locked
811 if (pkt->isRead() && pkt->req->isLLSC()) {
812 TheISA::handleLockedRead(thread, pkt->req);
813 }
814
815 delete pkt->req;
816 delete pkt;
817
818 postExecute();
819
820 if (getState() == SimObject::Draining) {
821 advancePC(fault);
822 completeDrain();
823
824 return;
825 }
826
827 advanceInst(fault);
828}
829
830
831void
832TimingSimpleCPU::completeDrain()
833{
|