1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Steve Reinhardt
29 */
30
31#include "arch/locked_mem.hh"
32#include "arch/mmaped_ipr.hh"
33#include "arch/utility.hh"
34#include "base/bigint.hh"
35#include "cpu/exetrace.hh"
36#include "cpu/simple/timing.hh"
37#include "mem/packet.hh"
38#include "mem/packet_access.hh"
39#include "params/TimingSimpleCPU.hh"
40#include "sim/system.hh"
41
42using namespace std;
43using namespace TheISA;
44
45Port *
46TimingSimpleCPU::getPort(const std::string &if_name, int idx)
47{
48 if (if_name == "dcache_port")
49 return &dcachePort;
50 else if (if_name == "icache_port")
51 return &icachePort;
52 else
53 panic("No Such Port\n");
54}
55
56void
57TimingSimpleCPU::init()
58{
59 BaseCPU::init();
60#if FULL_SYSTEM
61 for (int i = 0; i < threadContexts.size(); ++i) {
62 ThreadContext *tc = threadContexts[i];
63
64 // initialize CPU, including PC
65 TheISA::initCPU(tc, tc->readCpuId());
66 }
67#endif
68}
69
70Tick
71TimingSimpleCPU::CpuPort::recvAtomic(PacketPtr pkt)
72{
73 panic("TimingSimpleCPU doesn't expect recvAtomic callback!");
74 return curTick;
75}
76
77void
78TimingSimpleCPU::CpuPort::recvFunctional(PacketPtr pkt)
79{
80 //No internal storage to update, jusst return
81 return;
82}
83
84void
85TimingSimpleCPU::CpuPort::recvStatusChange(Status status)
86{
87 if (status == RangeChange) {
88 if (!snoopRangeSent) {
89 snoopRangeSent = true;
90 sendStatusChange(Port::RangeChange);
91 }
92 return;
93 }
94
95 panic("TimingSimpleCPU doesn't expect recvStatusChange callback!");
96}
97
98
99void
100TimingSimpleCPU::CpuPort::TickEvent::schedule(PacketPtr _pkt, Tick t)
101{
102 pkt = _pkt;
103 Event::schedule(t);
104}
105
106TimingSimpleCPU::TimingSimpleCPU(Params *p)
107 : BaseSimpleCPU(p), icachePort(this, p->clock), dcachePort(this, p->clock)
108{
109 _status = Idle;
110
111 icachePort.snoopRangeSent = false;
112 dcachePort.snoopRangeSent = false;
113
114 ifetch_pkt = dcache_pkt = NULL;
115 drainEvent = NULL;
116 fetchEvent = NULL;
117 previousTick = 0;
118 changeState(SimObject::Running);
119}
120
121
122TimingSimpleCPU::~TimingSimpleCPU()
123{
124}
125
126void
127TimingSimpleCPU::serialize(ostream &os)
128{
129 SimObject::State so_state = SimObject::getState();
130 SERIALIZE_ENUM(so_state);
131 BaseSimpleCPU::serialize(os);
132}
133
134void
135TimingSimpleCPU::unserialize(Checkpoint *cp, const string §ion)
136{
137 SimObject::State so_state;
138 UNSERIALIZE_ENUM(so_state);
139 BaseSimpleCPU::unserialize(cp, section);
140}
141
142unsigned int
143TimingSimpleCPU::drain(Event *drain_event)
144{
145 // TimingSimpleCPU is ready to drain if it's not waiting for
146 // an access to complete.
147 if (status() == Idle || status() == Running || status() == SwitchedOut) {
148 changeState(SimObject::Drained);
149 return 0;
150 } else {
151 changeState(SimObject::Draining);
152 drainEvent = drain_event;
153 return 1;
154 }
155}
156
157void
158TimingSimpleCPU::resume()
159{
| 1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Steve Reinhardt
29 */
30
31#include "arch/locked_mem.hh"
32#include "arch/mmaped_ipr.hh"
33#include "arch/utility.hh"
34#include "base/bigint.hh"
35#include "cpu/exetrace.hh"
36#include "cpu/simple/timing.hh"
37#include "mem/packet.hh"
38#include "mem/packet_access.hh"
39#include "params/TimingSimpleCPU.hh"
40#include "sim/system.hh"
41
42using namespace std;
43using namespace TheISA;
44
45Port *
46TimingSimpleCPU::getPort(const std::string &if_name, int idx)
47{
48 if (if_name == "dcache_port")
49 return &dcachePort;
50 else if (if_name == "icache_port")
51 return &icachePort;
52 else
53 panic("No Such Port\n");
54}
55
56void
57TimingSimpleCPU::init()
58{
59 BaseCPU::init();
60#if FULL_SYSTEM
61 for (int i = 0; i < threadContexts.size(); ++i) {
62 ThreadContext *tc = threadContexts[i];
63
64 // initialize CPU, including PC
65 TheISA::initCPU(tc, tc->readCpuId());
66 }
67#endif
68}
69
70Tick
71TimingSimpleCPU::CpuPort::recvAtomic(PacketPtr pkt)
72{
73 panic("TimingSimpleCPU doesn't expect recvAtomic callback!");
74 return curTick;
75}
76
77void
78TimingSimpleCPU::CpuPort::recvFunctional(PacketPtr pkt)
79{
80 //No internal storage to update, jusst return
81 return;
82}
83
84void
85TimingSimpleCPU::CpuPort::recvStatusChange(Status status)
86{
87 if (status == RangeChange) {
88 if (!snoopRangeSent) {
89 snoopRangeSent = true;
90 sendStatusChange(Port::RangeChange);
91 }
92 return;
93 }
94
95 panic("TimingSimpleCPU doesn't expect recvStatusChange callback!");
96}
97
98
99void
100TimingSimpleCPU::CpuPort::TickEvent::schedule(PacketPtr _pkt, Tick t)
101{
102 pkt = _pkt;
103 Event::schedule(t);
104}
105
106TimingSimpleCPU::TimingSimpleCPU(Params *p)
107 : BaseSimpleCPU(p), icachePort(this, p->clock), dcachePort(this, p->clock)
108{
109 _status = Idle;
110
111 icachePort.snoopRangeSent = false;
112 dcachePort.snoopRangeSent = false;
113
114 ifetch_pkt = dcache_pkt = NULL;
115 drainEvent = NULL;
116 fetchEvent = NULL;
117 previousTick = 0;
118 changeState(SimObject::Running);
119}
120
121
122TimingSimpleCPU::~TimingSimpleCPU()
123{
124}
125
126void
127TimingSimpleCPU::serialize(ostream &os)
128{
129 SimObject::State so_state = SimObject::getState();
130 SERIALIZE_ENUM(so_state);
131 BaseSimpleCPU::serialize(os);
132}
133
134void
135TimingSimpleCPU::unserialize(Checkpoint *cp, const string §ion)
136{
137 SimObject::State so_state;
138 UNSERIALIZE_ENUM(so_state);
139 BaseSimpleCPU::unserialize(cp, section);
140}
141
142unsigned int
143TimingSimpleCPU::drain(Event *drain_event)
144{
145 // TimingSimpleCPU is ready to drain if it's not waiting for
146 // an access to complete.
147 if (status() == Idle || status() == Running || status() == SwitchedOut) {
148 changeState(SimObject::Drained);
149 return 0;
150 } else {
151 changeState(SimObject::Draining);
152 drainEvent = drain_event;
153 return 1;
154 }
155}
156
157void
158TimingSimpleCPU::resume()
159{
|
234 assert(thread_num == 0);
235 assert(thread);
236
237 assert(_status == Running);
238
239 // just change status to Idle... if status != Running,
240 // completeInst() will not initiate fetch of next instruction.
241
242 notIdleFraction--;
243 _status = Idle;
244}
245
246
247template <class T>
248Fault
249TimingSimpleCPU::read(Addr addr, T &data, unsigned flags)
250{
251 Request *req =
252 new Request(/* asid */ 0, addr, sizeof(T), flags, thread->readPC(),
253 cpuId, /* thread ID */ 0);
254
255 if (traceData) {
256 traceData->setAddr(req->getVaddr());
257 }
258
259 // translate to physical address
260 Fault fault = thread->translateDataReadReq(req);
261
262 // Now do the access.
263 if (fault == NoFault) {
264 PacketPtr pkt =
265 new Packet(req,
266 (req->isLocked() ?
267 MemCmd::LoadLockedReq : MemCmd::ReadReq),
268 Packet::Broadcast);
269 pkt->dataDynamic<T>(new T);
270
271 if (req->isMmapedIpr()) {
272 Tick delay;
273 delay = TheISA::handleIprRead(thread->getTC(), pkt);
274 new IprEvent(pkt, this, nextCycle(curTick + delay));
275 _status = DcacheWaitResponse;
276 dcache_pkt = NULL;
277 } else if (!dcachePort.sendTiming(pkt)) {
278 _status = DcacheRetry;
279 dcache_pkt = pkt;
280 } else {
281 _status = DcacheWaitResponse;
282 // memory system takes ownership of packet
283 dcache_pkt = NULL;
284 }
285
286 // This will need a new way to tell if it has a dcache attached.
287 if (req->isUncacheable())
288 recordEvent("Uncached Read");
289 } else {
290 delete req;
291 }
292
293 return fault;
294}
295
296Fault
297TimingSimpleCPU::translateDataReadAddr(Addr vaddr, Addr &paddr,
298 int size, unsigned flags)
299{
300 Request *req =
301 new Request(0, vaddr, size, flags, thread->readPC(), cpuId, 0);
302
303 if (traceData) {
304 traceData->setAddr(vaddr);
305 }
306
307 Fault fault = thread->translateDataWriteReq(req);
308
309 if (fault == NoFault)
310 paddr = req->getPaddr();
311
312 delete req;
313 return fault;
314}
315
316#ifndef DOXYGEN_SHOULD_SKIP_THIS
317
318template
319Fault
320TimingSimpleCPU::read(Addr addr, Twin64_t &data, unsigned flags);
321
322template
323Fault
324TimingSimpleCPU::read(Addr addr, Twin32_t &data, unsigned flags);
325
326template
327Fault
328TimingSimpleCPU::read(Addr addr, uint64_t &data, unsigned flags);
329
330template
331Fault
332TimingSimpleCPU::read(Addr addr, uint32_t &data, unsigned flags);
333
334template
335Fault
336TimingSimpleCPU::read(Addr addr, uint16_t &data, unsigned flags);
337
338template
339Fault
340TimingSimpleCPU::read(Addr addr, uint8_t &data, unsigned flags);
341
342#endif //DOXYGEN_SHOULD_SKIP_THIS
343
344template<>
345Fault
346TimingSimpleCPU::read(Addr addr, double &data, unsigned flags)
347{
348 return read(addr, *(uint64_t*)&data, flags);
349}
350
351template<>
352Fault
353TimingSimpleCPU::read(Addr addr, float &data, unsigned flags)
354{
355 return read(addr, *(uint32_t*)&data, flags);
356}
357
358
359template<>
360Fault
361TimingSimpleCPU::read(Addr addr, int32_t &data, unsigned flags)
362{
363 return read(addr, (uint32_t&)data, flags);
364}
365
366
367template <class T>
368Fault
369TimingSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res)
370{
371 Request *req =
372 new Request(/* asid */ 0, addr, sizeof(T), flags, thread->readPC(),
373 cpuId, /* thread ID */ 0);
374
375 if (traceData) {
376 traceData->setAddr(req->getVaddr());
377 }
378
379 // translate to physical address
380 Fault fault = thread->translateDataWriteReq(req);
381
382 // Now do the access.
383 if (fault == NoFault) {
384 MemCmd cmd = MemCmd::WriteReq; // default
385 bool do_access = true; // flag to suppress cache access
386
387 if (req->isLocked()) {
388 cmd = MemCmd::StoreCondReq;
389 do_access = TheISA::handleLockedWrite(thread, req);
390 } else if (req->isSwap()) {
391 cmd = MemCmd::SwapReq;
392 if (req->isCondSwap()) {
393 assert(res);
394 req->setExtraData(*res);
395 }
396 }
397
398 // Note: need to allocate dcache_pkt even if do_access is
399 // false, as it's used unconditionally to call completeAcc().
400 assert(dcache_pkt == NULL);
401 dcache_pkt = new Packet(req, cmd, Packet::Broadcast);
402 dcache_pkt->allocate();
403 dcache_pkt->set(data);
404
405 if (do_access) {
406 if (req->isMmapedIpr()) {
407 Tick delay;
408 dcache_pkt->set(htog(data));
409 delay = TheISA::handleIprWrite(thread->getTC(), dcache_pkt);
410 new IprEvent(dcache_pkt, this, nextCycle(curTick + delay));
411 _status = DcacheWaitResponse;
412 dcache_pkt = NULL;
413 } else if (!dcachePort.sendTiming(dcache_pkt)) {
414 _status = DcacheRetry;
415 } else {
416 _status = DcacheWaitResponse;
417 // memory system takes ownership of packet
418 dcache_pkt = NULL;
419 }
420 }
421 // This will need a new way to tell if it's hooked up to a cache or not.
422 if (req->isUncacheable())
423 recordEvent("Uncached Write");
424 } else {
425 delete req;
426 }
427
428
429 // If the write needs to have a fault on the access, consider calling
430 // changeStatus() and changing it to "bad addr write" or something.
431 return fault;
432}
433
434Fault
435TimingSimpleCPU::translateDataWriteAddr(Addr vaddr, Addr &paddr,
436 int size, unsigned flags)
437{
438 Request *req =
439 new Request(0, vaddr, size, flags, thread->readPC(), cpuId, 0);
440
441 if (traceData) {
442 traceData->setAddr(vaddr);
443 }
444
445 Fault fault = thread->translateDataWriteReq(req);
446
447 if (fault == NoFault)
448 paddr = req->getPaddr();
449
450 delete req;
451 return fault;
452}
453
454
455#ifndef DOXYGEN_SHOULD_SKIP_THIS
456template
457Fault
458TimingSimpleCPU::write(Twin32_t data, Addr addr,
459 unsigned flags, uint64_t *res);
460
461template
462Fault
463TimingSimpleCPU::write(Twin64_t data, Addr addr,
464 unsigned flags, uint64_t *res);
465
466template
467Fault
468TimingSimpleCPU::write(uint64_t data, Addr addr,
469 unsigned flags, uint64_t *res);
470
471template
472Fault
473TimingSimpleCPU::write(uint32_t data, Addr addr,
474 unsigned flags, uint64_t *res);
475
476template
477Fault
478TimingSimpleCPU::write(uint16_t data, Addr addr,
479 unsigned flags, uint64_t *res);
480
481template
482Fault
483TimingSimpleCPU::write(uint8_t data, Addr addr,
484 unsigned flags, uint64_t *res);
485
486#endif //DOXYGEN_SHOULD_SKIP_THIS
487
488template<>
489Fault
490TimingSimpleCPU::write(double data, Addr addr, unsigned flags, uint64_t *res)
491{
492 return write(*(uint64_t*)&data, addr, flags, res);
493}
494
495template<>
496Fault
497TimingSimpleCPU::write(float data, Addr addr, unsigned flags, uint64_t *res)
498{
499 return write(*(uint32_t*)&data, addr, flags, res);
500}
501
502
503template<>
504Fault
505TimingSimpleCPU::write(int32_t data, Addr addr, unsigned flags, uint64_t *res)
506{
507 return write((uint32_t)data, addr, flags, res);
508}
509
510
511void
512TimingSimpleCPU::fetch()
513{
| 239 assert(thread_num == 0);
240 assert(thread);
241
242 assert(_status == Running);
243
244 // just change status to Idle... if status != Running,
245 // completeInst() will not initiate fetch of next instruction.
246
247 notIdleFraction--;
248 _status = Idle;
249}
250
251
252template <class T>
253Fault
254TimingSimpleCPU::read(Addr addr, T &data, unsigned flags)
255{
256 Request *req =
257 new Request(/* asid */ 0, addr, sizeof(T), flags, thread->readPC(),
258 cpuId, /* thread ID */ 0);
259
260 if (traceData) {
261 traceData->setAddr(req->getVaddr());
262 }
263
264 // translate to physical address
265 Fault fault = thread->translateDataReadReq(req);
266
267 // Now do the access.
268 if (fault == NoFault) {
269 PacketPtr pkt =
270 new Packet(req,
271 (req->isLocked() ?
272 MemCmd::LoadLockedReq : MemCmd::ReadReq),
273 Packet::Broadcast);
274 pkt->dataDynamic<T>(new T);
275
276 if (req->isMmapedIpr()) {
277 Tick delay;
278 delay = TheISA::handleIprRead(thread->getTC(), pkt);
279 new IprEvent(pkt, this, nextCycle(curTick + delay));
280 _status = DcacheWaitResponse;
281 dcache_pkt = NULL;
282 } else if (!dcachePort.sendTiming(pkt)) {
283 _status = DcacheRetry;
284 dcache_pkt = pkt;
285 } else {
286 _status = DcacheWaitResponse;
287 // memory system takes ownership of packet
288 dcache_pkt = NULL;
289 }
290
291 // This will need a new way to tell if it has a dcache attached.
292 if (req->isUncacheable())
293 recordEvent("Uncached Read");
294 } else {
295 delete req;
296 }
297
298 return fault;
299}
300
301Fault
302TimingSimpleCPU::translateDataReadAddr(Addr vaddr, Addr &paddr,
303 int size, unsigned flags)
304{
305 Request *req =
306 new Request(0, vaddr, size, flags, thread->readPC(), cpuId, 0);
307
308 if (traceData) {
309 traceData->setAddr(vaddr);
310 }
311
312 Fault fault = thread->translateDataWriteReq(req);
313
314 if (fault == NoFault)
315 paddr = req->getPaddr();
316
317 delete req;
318 return fault;
319}
320
321#ifndef DOXYGEN_SHOULD_SKIP_THIS
322
323template
324Fault
325TimingSimpleCPU::read(Addr addr, Twin64_t &data, unsigned flags);
326
327template
328Fault
329TimingSimpleCPU::read(Addr addr, Twin32_t &data, unsigned flags);
330
331template
332Fault
333TimingSimpleCPU::read(Addr addr, uint64_t &data, unsigned flags);
334
335template
336Fault
337TimingSimpleCPU::read(Addr addr, uint32_t &data, unsigned flags);
338
339template
340Fault
341TimingSimpleCPU::read(Addr addr, uint16_t &data, unsigned flags);
342
343template
344Fault
345TimingSimpleCPU::read(Addr addr, uint8_t &data, unsigned flags);
346
347#endif //DOXYGEN_SHOULD_SKIP_THIS
348
349template<>
350Fault
351TimingSimpleCPU::read(Addr addr, double &data, unsigned flags)
352{
353 return read(addr, *(uint64_t*)&data, flags);
354}
355
356template<>
357Fault
358TimingSimpleCPU::read(Addr addr, float &data, unsigned flags)
359{
360 return read(addr, *(uint32_t*)&data, flags);
361}
362
363
364template<>
365Fault
366TimingSimpleCPU::read(Addr addr, int32_t &data, unsigned flags)
367{
368 return read(addr, (uint32_t&)data, flags);
369}
370
371
372template <class T>
373Fault
374TimingSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res)
375{
376 Request *req =
377 new Request(/* asid */ 0, addr, sizeof(T), flags, thread->readPC(),
378 cpuId, /* thread ID */ 0);
379
380 if (traceData) {
381 traceData->setAddr(req->getVaddr());
382 }
383
384 // translate to physical address
385 Fault fault = thread->translateDataWriteReq(req);
386
387 // Now do the access.
388 if (fault == NoFault) {
389 MemCmd cmd = MemCmd::WriteReq; // default
390 bool do_access = true; // flag to suppress cache access
391
392 if (req->isLocked()) {
393 cmd = MemCmd::StoreCondReq;
394 do_access = TheISA::handleLockedWrite(thread, req);
395 } else if (req->isSwap()) {
396 cmd = MemCmd::SwapReq;
397 if (req->isCondSwap()) {
398 assert(res);
399 req->setExtraData(*res);
400 }
401 }
402
403 // Note: need to allocate dcache_pkt even if do_access is
404 // false, as it's used unconditionally to call completeAcc().
405 assert(dcache_pkt == NULL);
406 dcache_pkt = new Packet(req, cmd, Packet::Broadcast);
407 dcache_pkt->allocate();
408 dcache_pkt->set(data);
409
410 if (do_access) {
411 if (req->isMmapedIpr()) {
412 Tick delay;
413 dcache_pkt->set(htog(data));
414 delay = TheISA::handleIprWrite(thread->getTC(), dcache_pkt);
415 new IprEvent(dcache_pkt, this, nextCycle(curTick + delay));
416 _status = DcacheWaitResponse;
417 dcache_pkt = NULL;
418 } else if (!dcachePort.sendTiming(dcache_pkt)) {
419 _status = DcacheRetry;
420 } else {
421 _status = DcacheWaitResponse;
422 // memory system takes ownership of packet
423 dcache_pkt = NULL;
424 }
425 }
426 // This will need a new way to tell if it's hooked up to a cache or not.
427 if (req->isUncacheable())
428 recordEvent("Uncached Write");
429 } else {
430 delete req;
431 }
432
433
434 // If the write needs to have a fault on the access, consider calling
435 // changeStatus() and changing it to "bad addr write" or something.
436 return fault;
437}
438
439Fault
440TimingSimpleCPU::translateDataWriteAddr(Addr vaddr, Addr &paddr,
441 int size, unsigned flags)
442{
443 Request *req =
444 new Request(0, vaddr, size, flags, thread->readPC(), cpuId, 0);
445
446 if (traceData) {
447 traceData->setAddr(vaddr);
448 }
449
450 Fault fault = thread->translateDataWriteReq(req);
451
452 if (fault == NoFault)
453 paddr = req->getPaddr();
454
455 delete req;
456 return fault;
457}
458
459
460#ifndef DOXYGEN_SHOULD_SKIP_THIS
461template
462Fault
463TimingSimpleCPU::write(Twin32_t data, Addr addr,
464 unsigned flags, uint64_t *res);
465
466template
467Fault
468TimingSimpleCPU::write(Twin64_t data, Addr addr,
469 unsigned flags, uint64_t *res);
470
471template
472Fault
473TimingSimpleCPU::write(uint64_t data, Addr addr,
474 unsigned flags, uint64_t *res);
475
476template
477Fault
478TimingSimpleCPU::write(uint32_t data, Addr addr,
479 unsigned flags, uint64_t *res);
480
481template
482Fault
483TimingSimpleCPU::write(uint16_t data, Addr addr,
484 unsigned flags, uint64_t *res);
485
486template
487Fault
488TimingSimpleCPU::write(uint8_t data, Addr addr,
489 unsigned flags, uint64_t *res);
490
491#endif //DOXYGEN_SHOULD_SKIP_THIS
492
493template<>
494Fault
495TimingSimpleCPU::write(double data, Addr addr, unsigned flags, uint64_t *res)
496{
497 return write(*(uint64_t*)&data, addr, flags, res);
498}
499
500template<>
501Fault
502TimingSimpleCPU::write(float data, Addr addr, unsigned flags, uint64_t *res)
503{
504 return write(*(uint32_t*)&data, addr, flags, res);
505}
506
507
508template<>
509Fault
510TimingSimpleCPU::write(int32_t data, Addr addr, unsigned flags, uint64_t *res)
511{
512 return write((uint32_t)data, addr, flags, res);
513}
514
515
516void
517TimingSimpleCPU::fetch()
518{
|
563 // received a response from the icache: execute the received
564 // instruction
565 assert(!pkt->isError());
566 assert(_status == IcacheWaitResponse);
567
568 _status = Running;
569
570 numCycles += tickToCycles(curTick - previousTick);
571 previousTick = curTick;
572
573 if (getState() == SimObject::Draining) {
574 delete pkt->req;
575 delete pkt;
576
577 completeDrain();
578 return;
579 }
580
581 preExecute();
582 if (curStaticInst->isMemRef() && !curStaticInst->isDataPrefetch()) {
583 // load or store: just send to dcache
584 Fault fault = curStaticInst->initiateAcc(this, traceData);
585 if (_status != Running) {
586 // instruction will complete in dcache response callback
587 assert(_status == DcacheWaitResponse || _status == DcacheRetry);
588 assert(fault == NoFault);
589 } else {
590 if (fault == NoFault) {
591 // early fail on store conditional: complete now
592 assert(dcache_pkt != NULL);
593 fault = curStaticInst->completeAcc(dcache_pkt, this,
594 traceData);
595 delete dcache_pkt->req;
596 delete dcache_pkt;
597 dcache_pkt = NULL;
598
599 // keep an instruction count
600 if (fault == NoFault)
601 countInst();
602 } else if (traceData) {
603 // If there was a fault, we shouldn't trace this instruction.
604 delete traceData;
605 traceData = NULL;
606 }
607
608 postExecute();
609 // @todo remove me after debugging with legion done
610 if (curStaticInst && (!curStaticInst->isMicroop() ||
611 curStaticInst->isFirstMicroop()))
612 instCnt++;
613 advanceInst(fault);
614 }
615 } else {
616 // non-memory instruction: execute completely now
617 Fault fault = curStaticInst->execute(this, traceData);
618
619 // keep an instruction count
620 if (fault == NoFault)
621 countInst();
622 else if (traceData) {
623 // If there was a fault, we shouldn't trace this instruction.
624 delete traceData;
625 traceData = NULL;
626 }
627
628 postExecute();
629 // @todo remove me after debugging with legion done
630 if (curStaticInst && (!curStaticInst->isMicroop() ||
631 curStaticInst->isFirstMicroop()))
632 instCnt++;
633 advanceInst(fault);
634 }
635
636 delete pkt->req;
637 delete pkt;
638}
639
640void
641TimingSimpleCPU::IcachePort::ITickEvent::process()
642{
643 cpu->completeIfetch(pkt);
644}
645
646bool
647TimingSimpleCPU::IcachePort::recvTiming(PacketPtr pkt)
648{
649 if (pkt->isResponse() && !pkt->wasNacked()) {
650 // delay processing of returned data until next CPU clock edge
651 Tick next_tick = cpu->nextCycle(curTick);
652
653 if (next_tick == curTick)
654 cpu->completeIfetch(pkt);
655 else
656 tickEvent.schedule(pkt, next_tick);
657
658 return true;
659 }
660 else if (pkt->wasNacked()) {
661 assert(cpu->_status == IcacheWaitResponse);
662 pkt->reinitNacked();
663 if (!sendTiming(pkt)) {
664 cpu->_status = IcacheRetry;
665 cpu->ifetch_pkt = pkt;
666 }
667 }
668 //Snooping a Coherence Request, do nothing
669 return true;
670}
671
672void
673TimingSimpleCPU::IcachePort::recvRetry()
674{
675 // we shouldn't get a retry unless we have a packet that we're
676 // waiting to transmit
677 assert(cpu->ifetch_pkt != NULL);
678 assert(cpu->_status == IcacheRetry);
679 PacketPtr tmp = cpu->ifetch_pkt;
680 if (sendTiming(tmp)) {
681 cpu->_status = IcacheWaitResponse;
682 cpu->ifetch_pkt = NULL;
683 }
684}
685
686void
687TimingSimpleCPU::completeDataAccess(PacketPtr pkt)
688{
689 // received a response from the dcache: complete the load or store
690 // instruction
691 assert(!pkt->isError());
692 assert(_status == DcacheWaitResponse);
693 _status = Running;
694
695 numCycles += tickToCycles(curTick - previousTick);
696 previousTick = curTick;
697
698 Fault fault = curStaticInst->completeAcc(pkt, this, traceData);
699
700 // keep an instruction count
701 if (fault == NoFault)
702 countInst();
703 else if (traceData) {
704 // If there was a fault, we shouldn't trace this instruction.
705 delete traceData;
706 traceData = NULL;
707 }
708
709 if (pkt->isRead() && pkt->isLocked()) {
710 TheISA::handleLockedRead(thread, pkt->req);
711 }
712
713 delete pkt->req;
714 delete pkt;
715
716 postExecute();
717
718 if (getState() == SimObject::Draining) {
719 advancePC(fault);
720 completeDrain();
721
722 return;
723 }
724
725 advanceInst(fault);
726}
727
728
729void
730TimingSimpleCPU::completeDrain()
731{
732 DPRINTF(Config, "Done draining\n");
733 changeState(SimObject::Drained);
734 drainEvent->process();
735}
736
737void
738TimingSimpleCPU::DcachePort::setPeer(Port *port)
739{
740 Port::setPeer(port);
741
742#if FULL_SYSTEM
743 // Update the ThreadContext's memory ports (Functional/Virtual
744 // Ports)
745 cpu->tcBase()->connectMemPorts();
746#endif
747}
748
749bool
750TimingSimpleCPU::DcachePort::recvTiming(PacketPtr pkt)
751{
752 if (pkt->isResponse() && !pkt->wasNacked()) {
753 // delay processing of returned data until next CPU clock edge
754 Tick next_tick = cpu->nextCycle(curTick);
755
756 if (next_tick == curTick)
757 cpu->completeDataAccess(pkt);
758 else
759 tickEvent.schedule(pkt, next_tick);
760
761 return true;
762 }
763 else if (pkt->wasNacked()) {
764 assert(cpu->_status == DcacheWaitResponse);
765 pkt->reinitNacked();
766 if (!sendTiming(pkt)) {
767 cpu->_status = DcacheRetry;
768 cpu->dcache_pkt = pkt;
769 }
770 }
771 //Snooping a Coherence Request, do nothing
772 return true;
773}
774
775void
776TimingSimpleCPU::DcachePort::DTickEvent::process()
777{
778 cpu->completeDataAccess(pkt);
779}
780
781void
782TimingSimpleCPU::DcachePort::recvRetry()
783{
784 // we shouldn't get a retry unless we have a packet that we're
785 // waiting to transmit
786 assert(cpu->dcache_pkt != NULL);
787 assert(cpu->_status == DcacheRetry);
788 PacketPtr tmp = cpu->dcache_pkt;
789 if (sendTiming(tmp)) {
790 cpu->_status = DcacheWaitResponse;
791 // memory system takes ownership of packet
792 cpu->dcache_pkt = NULL;
793 }
794}
795
796TimingSimpleCPU::IprEvent::IprEvent(Packet *_pkt, TimingSimpleCPU *_cpu, Tick t)
797 : Event(&mainEventQueue), pkt(_pkt), cpu(_cpu)
798{
799 schedule(t);
800}
801
802void
803TimingSimpleCPU::IprEvent::process()
804{
805 cpu->completeDataAccess(pkt);
806}
807
808const char *
809TimingSimpleCPU::IprEvent::description()
810{
811 return "Timing Simple CPU Delay IPR event";
812}
813
814
815////////////////////////////////////////////////////////////////////////
816//
817// TimingSimpleCPU Simulation Object
818//
819TimingSimpleCPU *
820TimingSimpleCPUParams::create()
821{
822 TimingSimpleCPU::Params *params = new TimingSimpleCPU::Params();
823 params->name = name;
824 params->numberOfThreads = 1;
825 params->max_insts_any_thread = max_insts_any_thread;
826 params->max_insts_all_threads = max_insts_all_threads;
827 params->max_loads_any_thread = max_loads_any_thread;
828 params->max_loads_all_threads = max_loads_all_threads;
829 params->progress_interval = progress_interval;
830 params->deferRegistration = defer_registration;
831 params->clock = clock;
832 params->phase = phase;
833 params->functionTrace = function_trace;
834 params->functionTraceStart = function_trace_start;
835 params->system = system;
836 params->cpu_id = cpu_id;
837 params->tracer = tracer;
838
839 params->itb = itb;
840 params->dtb = dtb;
841#if FULL_SYSTEM
842 params->profile = profile;
843 params->do_quiesce = do_quiesce;
844 params->do_checkpoint_insts = do_checkpoint_insts;
845 params->do_statistics_insts = do_statistics_insts;
846#else
847 if (workload.size() != 1)
848 panic("only one workload allowed");
849 params->process = workload[0];
850#endif
851
852 TimingSimpleCPU *cpu = new TimingSimpleCPU(params);
853 return cpu;
854}
| 572 // received a response from the icache: execute the received
573 // instruction
574 assert(!pkt->isError());
575 assert(_status == IcacheWaitResponse);
576
577 _status = Running;
578
579 numCycles += tickToCycles(curTick - previousTick);
580 previousTick = curTick;
581
582 if (getState() == SimObject::Draining) {
583 delete pkt->req;
584 delete pkt;
585
586 completeDrain();
587 return;
588 }
589
590 preExecute();
591 if (curStaticInst->isMemRef() && !curStaticInst->isDataPrefetch()) {
592 // load or store: just send to dcache
593 Fault fault = curStaticInst->initiateAcc(this, traceData);
594 if (_status != Running) {
595 // instruction will complete in dcache response callback
596 assert(_status == DcacheWaitResponse || _status == DcacheRetry);
597 assert(fault == NoFault);
598 } else {
599 if (fault == NoFault) {
600 // early fail on store conditional: complete now
601 assert(dcache_pkt != NULL);
602 fault = curStaticInst->completeAcc(dcache_pkt, this,
603 traceData);
604 delete dcache_pkt->req;
605 delete dcache_pkt;
606 dcache_pkt = NULL;
607
608 // keep an instruction count
609 if (fault == NoFault)
610 countInst();
611 } else if (traceData) {
612 // If there was a fault, we shouldn't trace this instruction.
613 delete traceData;
614 traceData = NULL;
615 }
616
617 postExecute();
618 // @todo remove me after debugging with legion done
619 if (curStaticInst && (!curStaticInst->isMicroop() ||
620 curStaticInst->isFirstMicroop()))
621 instCnt++;
622 advanceInst(fault);
623 }
624 } else {
625 // non-memory instruction: execute completely now
626 Fault fault = curStaticInst->execute(this, traceData);
627
628 // keep an instruction count
629 if (fault == NoFault)
630 countInst();
631 else if (traceData) {
632 // If there was a fault, we shouldn't trace this instruction.
633 delete traceData;
634 traceData = NULL;
635 }
636
637 postExecute();
638 // @todo remove me after debugging with legion done
639 if (curStaticInst && (!curStaticInst->isMicroop() ||
640 curStaticInst->isFirstMicroop()))
641 instCnt++;
642 advanceInst(fault);
643 }
644
645 delete pkt->req;
646 delete pkt;
647}
648
649void
650TimingSimpleCPU::IcachePort::ITickEvent::process()
651{
652 cpu->completeIfetch(pkt);
653}
654
655bool
656TimingSimpleCPU::IcachePort::recvTiming(PacketPtr pkt)
657{
658 if (pkt->isResponse() && !pkt->wasNacked()) {
659 // delay processing of returned data until next CPU clock edge
660 Tick next_tick = cpu->nextCycle(curTick);
661
662 if (next_tick == curTick)
663 cpu->completeIfetch(pkt);
664 else
665 tickEvent.schedule(pkt, next_tick);
666
667 return true;
668 }
669 else if (pkt->wasNacked()) {
670 assert(cpu->_status == IcacheWaitResponse);
671 pkt->reinitNacked();
672 if (!sendTiming(pkt)) {
673 cpu->_status = IcacheRetry;
674 cpu->ifetch_pkt = pkt;
675 }
676 }
677 //Snooping a Coherence Request, do nothing
678 return true;
679}
680
681void
682TimingSimpleCPU::IcachePort::recvRetry()
683{
684 // we shouldn't get a retry unless we have a packet that we're
685 // waiting to transmit
686 assert(cpu->ifetch_pkt != NULL);
687 assert(cpu->_status == IcacheRetry);
688 PacketPtr tmp = cpu->ifetch_pkt;
689 if (sendTiming(tmp)) {
690 cpu->_status = IcacheWaitResponse;
691 cpu->ifetch_pkt = NULL;
692 }
693}
694
695void
696TimingSimpleCPU::completeDataAccess(PacketPtr pkt)
697{
698 // received a response from the dcache: complete the load or store
699 // instruction
700 assert(!pkt->isError());
701 assert(_status == DcacheWaitResponse);
702 _status = Running;
703
704 numCycles += tickToCycles(curTick - previousTick);
705 previousTick = curTick;
706
707 Fault fault = curStaticInst->completeAcc(pkt, this, traceData);
708
709 // keep an instruction count
710 if (fault == NoFault)
711 countInst();
712 else if (traceData) {
713 // If there was a fault, we shouldn't trace this instruction.
714 delete traceData;
715 traceData = NULL;
716 }
717
718 if (pkt->isRead() && pkt->isLocked()) {
719 TheISA::handleLockedRead(thread, pkt->req);
720 }
721
722 delete pkt->req;
723 delete pkt;
724
725 postExecute();
726
727 if (getState() == SimObject::Draining) {
728 advancePC(fault);
729 completeDrain();
730
731 return;
732 }
733
734 advanceInst(fault);
735}
736
737
738void
739TimingSimpleCPU::completeDrain()
740{
741 DPRINTF(Config, "Done draining\n");
742 changeState(SimObject::Drained);
743 drainEvent->process();
744}
745
746void
747TimingSimpleCPU::DcachePort::setPeer(Port *port)
748{
749 Port::setPeer(port);
750
751#if FULL_SYSTEM
752 // Update the ThreadContext's memory ports (Functional/Virtual
753 // Ports)
754 cpu->tcBase()->connectMemPorts();
755#endif
756}
757
758bool
759TimingSimpleCPU::DcachePort::recvTiming(PacketPtr pkt)
760{
761 if (pkt->isResponse() && !pkt->wasNacked()) {
762 // delay processing of returned data until next CPU clock edge
763 Tick next_tick = cpu->nextCycle(curTick);
764
765 if (next_tick == curTick)
766 cpu->completeDataAccess(pkt);
767 else
768 tickEvent.schedule(pkt, next_tick);
769
770 return true;
771 }
772 else if (pkt->wasNacked()) {
773 assert(cpu->_status == DcacheWaitResponse);
774 pkt->reinitNacked();
775 if (!sendTiming(pkt)) {
776 cpu->_status = DcacheRetry;
777 cpu->dcache_pkt = pkt;
778 }
779 }
780 //Snooping a Coherence Request, do nothing
781 return true;
782}
783
784void
785TimingSimpleCPU::DcachePort::DTickEvent::process()
786{
787 cpu->completeDataAccess(pkt);
788}
789
790void
791TimingSimpleCPU::DcachePort::recvRetry()
792{
793 // we shouldn't get a retry unless we have a packet that we're
794 // waiting to transmit
795 assert(cpu->dcache_pkt != NULL);
796 assert(cpu->_status == DcacheRetry);
797 PacketPtr tmp = cpu->dcache_pkt;
798 if (sendTiming(tmp)) {
799 cpu->_status = DcacheWaitResponse;
800 // memory system takes ownership of packet
801 cpu->dcache_pkt = NULL;
802 }
803}
804
805TimingSimpleCPU::IprEvent::IprEvent(Packet *_pkt, TimingSimpleCPU *_cpu, Tick t)
806 : Event(&mainEventQueue), pkt(_pkt), cpu(_cpu)
807{
808 schedule(t);
809}
810
811void
812TimingSimpleCPU::IprEvent::process()
813{
814 cpu->completeDataAccess(pkt);
815}
816
817const char *
818TimingSimpleCPU::IprEvent::description()
819{
820 return "Timing Simple CPU Delay IPR event";
821}
822
823
824////////////////////////////////////////////////////////////////////////
825//
826// TimingSimpleCPU Simulation Object
827//
828TimingSimpleCPU *
829TimingSimpleCPUParams::create()
830{
831 TimingSimpleCPU::Params *params = new TimingSimpleCPU::Params();
832 params->name = name;
833 params->numberOfThreads = 1;
834 params->max_insts_any_thread = max_insts_any_thread;
835 params->max_insts_all_threads = max_insts_all_threads;
836 params->max_loads_any_thread = max_loads_any_thread;
837 params->max_loads_all_threads = max_loads_all_threads;
838 params->progress_interval = progress_interval;
839 params->deferRegistration = defer_registration;
840 params->clock = clock;
841 params->phase = phase;
842 params->functionTrace = function_trace;
843 params->functionTraceStart = function_trace_start;
844 params->system = system;
845 params->cpu_id = cpu_id;
846 params->tracer = tracer;
847
848 params->itb = itb;
849 params->dtb = dtb;
850#if FULL_SYSTEM
851 params->profile = profile;
852 params->do_quiesce = do_quiesce;
853 params->do_checkpoint_insts = do_checkpoint_insts;
854 params->do_statistics_insts = do_statistics_insts;
855#else
856 if (workload.size() != 1)
857 panic("only one workload allowed");
858 params->process = workload[0];
859#endif
860
861 TimingSimpleCPU *cpu = new TimingSimpleCPU(params);
862 return cpu;
863}
|