1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Steve Reinhardt
29 */
30
31#include "arch/utility.hh"
32#include "cpu/exetrace.hh"
33#include "cpu/simple/timing.hh"
34#include "mem/packet_impl.hh"
35#include "sim/builder.hh"
36#include "sim/system.hh"
37
38using namespace std;
39using namespace TheISA;
40
41Port *
42TimingSimpleCPU::getPort(const std::string &if_name, int idx)
43{
44 if (if_name == "dcache_port")
45 return &dcachePort;
46 else if (if_name == "icache_port")
47 return &icachePort;
48 else
49 panic("No Such Port\n");
50}
51
52void
53TimingSimpleCPU::init()
54{
55 BaseCPU::init();
56#if FULL_SYSTEM
57 for (int i = 0; i < threadContexts.size(); ++i) {
58 ThreadContext *tc = threadContexts[i];
59
60 // initialize CPU, including PC
61 TheISA::initCPU(tc, tc->readCpuId());
62 }
63#endif
64}
65
66Tick
67TimingSimpleCPU::CpuPort::recvAtomic(Packet *pkt)
68{
69 panic("TimingSimpleCPU doesn't expect recvAtomic callback!");
70 return curTick;
71}
72
73void
74TimingSimpleCPU::CpuPort::recvFunctional(Packet *pkt)
75{
76 panic("TimingSimpleCPU doesn't expect recvFunctional callback!");
77}
78
79void
80TimingSimpleCPU::CpuPort::recvStatusChange(Status status)
81{
82 if (status == RangeChange)
83 return;
84
85 panic("TimingSimpleCPU doesn't expect recvStatusChange callback!");
86}
87
88
89void
90TimingSimpleCPU::CpuPort::TickEvent::schedule(Packet *_pkt, Tick t)
91{
92 pkt = _pkt;
93 Event::schedule(t);
94}
95
96TimingSimpleCPU::TimingSimpleCPU(Params *p)
97 : BaseSimpleCPU(p), icachePort(this, p->clock), dcachePort(this, p->clock)
98{
99 _status = Idle;
100 ifetch_pkt = dcache_pkt = NULL;
101 drainEvent = NULL;
102 fetchEvent = NULL;
103 changeState(SimObject::Running);
104}
105
106
107TimingSimpleCPU::~TimingSimpleCPU()
108{
109}
110
111void
112TimingSimpleCPU::serialize(ostream &os)
113{
114 SimObject::State so_state = SimObject::getState();
115 SERIALIZE_ENUM(so_state);
116 BaseSimpleCPU::serialize(os);
117}
118
119void
120TimingSimpleCPU::unserialize(Checkpoint *cp, const string §ion)
121{
122 SimObject::State so_state;
123 UNSERIALIZE_ENUM(so_state);
124 BaseSimpleCPU::unserialize(cp, section);
125}
126
127unsigned int
128TimingSimpleCPU::drain(Event *drain_event)
129{
130 // TimingSimpleCPU is ready to drain if it's not waiting for
131 // an access to complete.
132 if (status() == Idle || status() == Running || status() == SwitchedOut) {
133 changeState(SimObject::Drained);
134 return 0;
135 } else {
136 changeState(SimObject::Draining);
137 drainEvent = drain_event;
138 return 1;
139 }
140}
141
142void
143TimingSimpleCPU::resume()
144{
145 if (_status != SwitchedOut && _status != Idle) {
146 // Delete the old event if it existed.
147 if (fetchEvent) {
148 if (fetchEvent->scheduled())
149 fetchEvent->deschedule();
150
151 delete fetchEvent;
152 }
153
154 fetchEvent =
155 new EventWrapper<TimingSimpleCPU, &TimingSimpleCPU::fetch>(this, false);
156 fetchEvent->schedule(curTick);
157 }
158
159 assert(system->getMemoryMode() == System::Timing);
160 changeState(SimObject::Running);
161}
162
163void
164TimingSimpleCPU::switchOut()
165{
166 assert(status() == Running || status() == Idle);
167 _status = SwitchedOut;
168
169 // If we've been scheduled to resume but are then told to switch out,
170 // we'll need to cancel it.
171 if (fetchEvent && fetchEvent->scheduled())
172 fetchEvent->deschedule();
173}
174
175
176void
177TimingSimpleCPU::takeOverFrom(BaseCPU *oldCPU)
178{
179 BaseCPU::takeOverFrom(oldCPU);
180
181 // if any of this CPU's ThreadContexts are active, mark the CPU as
182 // running and schedule its tick event.
183 for (int i = 0; i < threadContexts.size(); ++i) {
184 ThreadContext *tc = threadContexts[i];
185 if (tc->status() == ThreadContext::Active && _status != Running) {
186 _status = Running;
187 break;
188 }
189 }
190}
191
192
193void
194TimingSimpleCPU::activateContext(int thread_num, int delay)
195{
196 assert(thread_num == 0);
197 assert(thread);
198
199 assert(_status == Idle);
200
201 notIdleFraction++;
202 _status = Running;
203 // kick things off by initiating the fetch of the next instruction
204 fetchEvent =
205 new EventWrapper<TimingSimpleCPU, &TimingSimpleCPU::fetch>(this, false);
206 fetchEvent->schedule(curTick + cycles(delay));
207}
208
209
210void
211TimingSimpleCPU::suspendContext(int thread_num)
212{
213 assert(thread_num == 0);
214 assert(thread);
215
216 assert(_status == Running);
217
218 // just change status to Idle... if status != Running,
219 // completeInst() will not initiate fetch of next instruction.
220
221 notIdleFraction--;
222 _status = Idle;
223}
224
225
226template <class T>
227Fault
228TimingSimpleCPU::read(Addr addr, T &data, unsigned flags)
229{
| 1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Steve Reinhardt
29 */
30
31#include "arch/utility.hh"
32#include "cpu/exetrace.hh"
33#include "cpu/simple/timing.hh"
34#include "mem/packet_impl.hh"
35#include "sim/builder.hh"
36#include "sim/system.hh"
37
38using namespace std;
39using namespace TheISA;
40
41Port *
42TimingSimpleCPU::getPort(const std::string &if_name, int idx)
43{
44 if (if_name == "dcache_port")
45 return &dcachePort;
46 else if (if_name == "icache_port")
47 return &icachePort;
48 else
49 panic("No Such Port\n");
50}
51
52void
53TimingSimpleCPU::init()
54{
55 BaseCPU::init();
56#if FULL_SYSTEM
57 for (int i = 0; i < threadContexts.size(); ++i) {
58 ThreadContext *tc = threadContexts[i];
59
60 // initialize CPU, including PC
61 TheISA::initCPU(tc, tc->readCpuId());
62 }
63#endif
64}
65
66Tick
67TimingSimpleCPU::CpuPort::recvAtomic(Packet *pkt)
68{
69 panic("TimingSimpleCPU doesn't expect recvAtomic callback!");
70 return curTick;
71}
72
73void
74TimingSimpleCPU::CpuPort::recvFunctional(Packet *pkt)
75{
76 panic("TimingSimpleCPU doesn't expect recvFunctional callback!");
77}
78
79void
80TimingSimpleCPU::CpuPort::recvStatusChange(Status status)
81{
82 if (status == RangeChange)
83 return;
84
85 panic("TimingSimpleCPU doesn't expect recvStatusChange callback!");
86}
87
88
89void
90TimingSimpleCPU::CpuPort::TickEvent::schedule(Packet *_pkt, Tick t)
91{
92 pkt = _pkt;
93 Event::schedule(t);
94}
95
96TimingSimpleCPU::TimingSimpleCPU(Params *p)
97 : BaseSimpleCPU(p), icachePort(this, p->clock), dcachePort(this, p->clock)
98{
99 _status = Idle;
100 ifetch_pkt = dcache_pkt = NULL;
101 drainEvent = NULL;
102 fetchEvent = NULL;
103 changeState(SimObject::Running);
104}
105
106
107TimingSimpleCPU::~TimingSimpleCPU()
108{
109}
110
111void
112TimingSimpleCPU::serialize(ostream &os)
113{
114 SimObject::State so_state = SimObject::getState();
115 SERIALIZE_ENUM(so_state);
116 BaseSimpleCPU::serialize(os);
117}
118
119void
120TimingSimpleCPU::unserialize(Checkpoint *cp, const string §ion)
121{
122 SimObject::State so_state;
123 UNSERIALIZE_ENUM(so_state);
124 BaseSimpleCPU::unserialize(cp, section);
125}
126
127unsigned int
128TimingSimpleCPU::drain(Event *drain_event)
129{
130 // TimingSimpleCPU is ready to drain if it's not waiting for
131 // an access to complete.
132 if (status() == Idle || status() == Running || status() == SwitchedOut) {
133 changeState(SimObject::Drained);
134 return 0;
135 } else {
136 changeState(SimObject::Draining);
137 drainEvent = drain_event;
138 return 1;
139 }
140}
141
142void
143TimingSimpleCPU::resume()
144{
145 if (_status != SwitchedOut && _status != Idle) {
146 // Delete the old event if it existed.
147 if (fetchEvent) {
148 if (fetchEvent->scheduled())
149 fetchEvent->deschedule();
150
151 delete fetchEvent;
152 }
153
154 fetchEvent =
155 new EventWrapper<TimingSimpleCPU, &TimingSimpleCPU::fetch>(this, false);
156 fetchEvent->schedule(curTick);
157 }
158
159 assert(system->getMemoryMode() == System::Timing);
160 changeState(SimObject::Running);
161}
162
163void
164TimingSimpleCPU::switchOut()
165{
166 assert(status() == Running || status() == Idle);
167 _status = SwitchedOut;
168
169 // If we've been scheduled to resume but are then told to switch out,
170 // we'll need to cancel it.
171 if (fetchEvent && fetchEvent->scheduled())
172 fetchEvent->deschedule();
173}
174
175
176void
177TimingSimpleCPU::takeOverFrom(BaseCPU *oldCPU)
178{
179 BaseCPU::takeOverFrom(oldCPU);
180
181 // if any of this CPU's ThreadContexts are active, mark the CPU as
182 // running and schedule its tick event.
183 for (int i = 0; i < threadContexts.size(); ++i) {
184 ThreadContext *tc = threadContexts[i];
185 if (tc->status() == ThreadContext::Active && _status != Running) {
186 _status = Running;
187 break;
188 }
189 }
190}
191
192
193void
194TimingSimpleCPU::activateContext(int thread_num, int delay)
195{
196 assert(thread_num == 0);
197 assert(thread);
198
199 assert(_status == Idle);
200
201 notIdleFraction++;
202 _status = Running;
203 // kick things off by initiating the fetch of the next instruction
204 fetchEvent =
205 new EventWrapper<TimingSimpleCPU, &TimingSimpleCPU::fetch>(this, false);
206 fetchEvent->schedule(curTick + cycles(delay));
207}
208
209
210void
211TimingSimpleCPU::suspendContext(int thread_num)
212{
213 assert(thread_num == 0);
214 assert(thread);
215
216 assert(_status == Running);
217
218 // just change status to Idle... if status != Running,
219 // completeInst() will not initiate fetch of next instruction.
220
221 notIdleFraction--;
222 _status = Idle;
223}
224
225
226template <class T>
227Fault
228TimingSimpleCPU::read(Addr addr, T &data, unsigned flags)
229{
|
230 // need to fill in CPU & thread IDs here
231 Request *data_read_req = new Request();
232 data_read_req->setThreadContext(0,0); //Need CPU/Thread IDS HERE
233 data_read_req->setVirt(0, addr, sizeof(T), flags, thread->readPC());
| 230 Request *req =
231 new Request(/* asid */ 0, addr, sizeof(T), flags, thread->readPC(),
232 /* CPU ID */ 0, /* thread ID */ 0);
|
234
235 if (traceData) {
| 233
234 if (traceData) {
|
236 traceData->setAddr(data_read_req->getVaddr());
| 235 traceData->setAddr(req->getVaddr());
|
237 }
238
239 // translate to physical address
| 236 }
237
238 // translate to physical address
|
240 Fault fault = thread->translateDataReadReq(data_read_req);
| 239 Fault fault = thread->translateDataReadReq(req);
|
241
242 // Now do the access.
243 if (fault == NoFault) {
| 240
241 // Now do the access.
242 if (fault == NoFault) {
|
244 Packet *data_read_pkt =
245 new Packet(data_read_req, Packet::ReadReq, Packet::Broadcast);
246 data_read_pkt->dataDynamic<T>(new T);
| 243 Packet *pkt =
244 new Packet(req, Packet::ReadReq, Packet::Broadcast);
245 pkt->dataDynamic(new T);
|
247
| 246
|
248 if (!dcachePort.sendTiming(data_read_pkt)) {
| 247 if (!dcachePort.sendTiming(pkt)) {
|
249 _status = DcacheRetry;
| 248 _status = DcacheRetry;
|
250 dcache_pkt = data_read_pkt;
| 249 dcache_pkt = pkt;
|
251 } else {
252 _status = DcacheWaitResponse;
| 250 } else {
251 _status = DcacheWaitResponse;
|
| 252 // memory system takes ownership of packet
|
253 dcache_pkt = NULL;
254 }
255 }
256
257 // This will need a new way to tell if it has a dcache attached.
| 253 dcache_pkt = NULL;
254 }
255 }
256
257 // This will need a new way to tell if it has a dcache attached.
|
258 if (data_read_req->getFlags() & UNCACHEABLE)
| 258 if (req->getFlags() & UNCACHEABLE)
|
259 recordEvent("Uncached Read");
260
261 return fault;
262}
263
264#ifndef DOXYGEN_SHOULD_SKIP_THIS
265
266template
267Fault
268TimingSimpleCPU::read(Addr addr, uint64_t &data, unsigned flags);
269
270template
271Fault
272TimingSimpleCPU::read(Addr addr, uint32_t &data, unsigned flags);
273
274template
275Fault
276TimingSimpleCPU::read(Addr addr, uint16_t &data, unsigned flags);
277
278template
279Fault
280TimingSimpleCPU::read(Addr addr, uint8_t &data, unsigned flags);
281
282#endif //DOXYGEN_SHOULD_SKIP_THIS
283
284template<>
285Fault
286TimingSimpleCPU::read(Addr addr, double &data, unsigned flags)
287{
288 return read(addr, *(uint64_t*)&data, flags);
289}
290
291template<>
292Fault
293TimingSimpleCPU::read(Addr addr, float &data, unsigned flags)
294{
295 return read(addr, *(uint32_t*)&data, flags);
296}
297
298
299template<>
300Fault
301TimingSimpleCPU::read(Addr addr, int32_t &data, unsigned flags)
302{
303 return read(addr, (uint32_t&)data, flags);
304}
305
306
307template <class T>
308Fault
309TimingSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res)
310{
| 259 recordEvent("Uncached Read");
260
261 return fault;
262}
263
264#ifndef DOXYGEN_SHOULD_SKIP_THIS
265
266template
267Fault
268TimingSimpleCPU::read(Addr addr, uint64_t &data, unsigned flags);
269
270template
271Fault
272TimingSimpleCPU::read(Addr addr, uint32_t &data, unsigned flags);
273
274template
275Fault
276TimingSimpleCPU::read(Addr addr, uint16_t &data, unsigned flags);
277
278template
279Fault
280TimingSimpleCPU::read(Addr addr, uint8_t &data, unsigned flags);
281
282#endif //DOXYGEN_SHOULD_SKIP_THIS
283
284template<>
285Fault
286TimingSimpleCPU::read(Addr addr, double &data, unsigned flags)
287{
288 return read(addr, *(uint64_t*)&data, flags);
289}
290
291template<>
292Fault
293TimingSimpleCPU::read(Addr addr, float &data, unsigned flags)
294{
295 return read(addr, *(uint32_t*)&data, flags);
296}
297
298
299template<>
300Fault
301TimingSimpleCPU::read(Addr addr, int32_t &data, unsigned flags)
302{
303 return read(addr, (uint32_t&)data, flags);
304}
305
306
307template <class T>
308Fault
309TimingSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res)
310{
|
311 // need to fill in CPU & thread IDs here
312 Request *data_write_req = new Request();
313 data_write_req->setThreadContext(0,0); //Need CPU/Thread IDS HERE
314 data_write_req->setVirt(0, addr, sizeof(T), flags, thread->readPC());
| 311 Request *req =
312 new Request(/* asid */ 0, addr, sizeof(T), flags, thread->readPC(),
313 /* CPU ID */ 0, /* thread ID */ 0);
|
315
316 // translate to physical address
| 314
315 // translate to physical address
|
317 Fault fault = thread->translateDataWriteReq(data_write_req);
| 316 Fault fault = thread->translateDataWriteReq(req);
317
|
318 // Now do the access.
319 if (fault == NoFault) {
| 318 // Now do the access.
319 if (fault == NoFault) {
|
320 Packet *data_write_pkt =
321 new Packet(data_write_req, Packet::WriteReq, Packet::Broadcast);
322 data_write_pkt->allocate();
323 data_write_pkt->set(data);
| 320 assert(dcache_pkt == NULL);
321 dcache_pkt = new Packet(req, Packet::WriteReq, Packet::Broadcast);
322 dcache_pkt->allocate();
323 dcache_pkt->set(data);
|
324
| 324
|
325 if (!dcachePort.sendTiming(data_write_pkt)) {
| 325 if (!dcachePort.sendTiming(dcache_pkt)) {
|
326 _status = DcacheRetry;
| 326 _status = DcacheRetry;
|
327 dcache_pkt = data_write_pkt;
| |
328 } else {
329 _status = DcacheWaitResponse;
| 327 } else {
328 _status = DcacheWaitResponse;
|
| 329 // memory system takes ownership of packet
|
330 dcache_pkt = NULL;
331 }
332 }
333
334 // This will need a new way to tell if it's hooked up to a cache or not.
| 330 dcache_pkt = NULL;
331 }
332 }
333
334 // This will need a new way to tell if it's hooked up to a cache or not.
|
335 if (data_write_req->getFlags() & UNCACHEABLE)
| 335 if (req->getFlags() & UNCACHEABLE)
|
336 recordEvent("Uncached Write");
337
338 // If the write needs to have a fault on the access, consider calling
339 // changeStatus() and changing it to "bad addr write" or something.
340 return fault;
341}
342
343
344#ifndef DOXYGEN_SHOULD_SKIP_THIS
345template
346Fault
347TimingSimpleCPU::write(uint64_t data, Addr addr,
348 unsigned flags, uint64_t *res);
349
350template
351Fault
352TimingSimpleCPU::write(uint32_t data, Addr addr,
353 unsigned flags, uint64_t *res);
354
355template
356Fault
357TimingSimpleCPU::write(uint16_t data, Addr addr,
358 unsigned flags, uint64_t *res);
359
360template
361Fault
362TimingSimpleCPU::write(uint8_t data, Addr addr,
363 unsigned flags, uint64_t *res);
364
365#endif //DOXYGEN_SHOULD_SKIP_THIS
366
367template<>
368Fault
369TimingSimpleCPU::write(double data, Addr addr, unsigned flags, uint64_t *res)
370{
371 return write(*(uint64_t*)&data, addr, flags, res);
372}
373
374template<>
375Fault
376TimingSimpleCPU::write(float data, Addr addr, unsigned flags, uint64_t *res)
377{
378 return write(*(uint32_t*)&data, addr, flags, res);
379}
380
381
382template<>
383Fault
384TimingSimpleCPU::write(int32_t data, Addr addr, unsigned flags, uint64_t *res)
385{
386 return write((uint32_t)data, addr, flags, res);
387}
388
389
390void
391TimingSimpleCPU::fetch()
392{
393 checkForInterrupts();
394
395 // need to fill in CPU & thread IDs here
396 Request *ifetch_req = new Request();
397 ifetch_req->setThreadContext(0,0); //Need CPU/Thread IDS HERE
398 Fault fault = setupFetchRequest(ifetch_req);
399
400 ifetch_pkt = new Packet(ifetch_req, Packet::ReadReq, Packet::Broadcast);
401 ifetch_pkt->dataStatic(&inst);
402
403 if (fault == NoFault) {
404 if (!icachePort.sendTiming(ifetch_pkt)) {
405 // Need to wait for retry
406 _status = IcacheRetry;
407 } else {
408 // Need to wait for cache to respond
409 _status = IcacheWaitResponse;
410 // ownership of packet transferred to memory system
411 ifetch_pkt = NULL;
412 }
413 } else {
414 // fetch fault: advance directly to next instruction (fault handler)
415 advanceInst(fault);
416 }
417}
418
419
420void
421TimingSimpleCPU::advanceInst(Fault fault)
422{
423 advancePC(fault);
424
425 if (_status == Running) {
426 // kick off fetch of next instruction... callback from icache
427 // response will cause that instruction to be executed,
428 // keeping the CPU running.
429 fetch();
430 }
431}
432
433
434void
435TimingSimpleCPU::completeIfetch(Packet *pkt)
436{
437 // received a response from the icache: execute the received
438 // instruction
439 assert(pkt->result == Packet::Success);
440 assert(_status == IcacheWaitResponse);
441
442 _status = Running;
443
444 delete pkt->req;
445 delete pkt;
446
447 if (getState() == SimObject::Draining) {
448 completeDrain();
449 return;
450 }
451
452 preExecute();
453 if (curStaticInst->isMemRef() && !curStaticInst->isDataPrefetch()) {
454 // load or store: just send to dcache
455 Fault fault = curStaticInst->initiateAcc(this, traceData);
456 if (fault == NoFault) {
457 // successfully initiated access: instruction will
458 // complete in dcache response callback
459 assert(_status == DcacheWaitResponse);
460 } else {
461 // fault: complete now to invoke fault handler
462 postExecute();
463 advanceInst(fault);
464 }
465 } else {
466 // non-memory instruction: execute completely now
467 Fault fault = curStaticInst->execute(this, traceData);
468 postExecute();
469 advanceInst(fault);
470 }
471}
472
473void
474TimingSimpleCPU::IcachePort::ITickEvent::process()
475{
476 cpu->completeIfetch(pkt);
477}
478
479bool
480TimingSimpleCPU::IcachePort::recvTiming(Packet *pkt)
481{
482 // These next few lines could be replaced with something faster
483 // who knows what though
484 Tick time = pkt->req->getTime();
485 while (time < curTick)
486 time += lat;
487
488 if (time == curTick)
489 cpu->completeIfetch(pkt);
490 else
491 tickEvent.schedule(pkt, time);
492
493 return true;
494}
495
496void
497TimingSimpleCPU::IcachePort::recvRetry()
498{
499 // we shouldn't get a retry unless we have a packet that we're
500 // waiting to transmit
501 assert(cpu->ifetch_pkt != NULL);
502 assert(cpu->_status == IcacheRetry);
503 Packet *tmp = cpu->ifetch_pkt;
504 if (sendTiming(tmp)) {
505 cpu->_status = IcacheWaitResponse;
506 cpu->ifetch_pkt = NULL;
507 }
508}
509
510void
511TimingSimpleCPU::completeDataAccess(Packet *pkt)
512{
513 // received a response from the dcache: complete the load or store
514 // instruction
515 assert(pkt->result == Packet::Success);
516 assert(_status == DcacheWaitResponse);
517 _status = Running;
518
519 if (getState() == SimObject::Draining) {
520 completeDrain();
521
522 delete pkt->req;
523 delete pkt;
524
525 return;
526 }
527
528 Fault fault = curStaticInst->completeAcc(pkt, this, traceData);
529
530 delete pkt->req;
531 delete pkt;
532
533 postExecute();
534 advanceInst(fault);
535}
536
537
538void
539TimingSimpleCPU::completeDrain()
540{
541 DPRINTF(Config, "Done draining\n");
542 changeState(SimObject::Drained);
543 drainEvent->process();
544}
545
546bool
547TimingSimpleCPU::DcachePort::recvTiming(Packet *pkt)
548{
549 Tick time = pkt->req->getTime();
550 while (time < curTick)
551 time += lat;
552
553 if (time == curTick)
554 cpu->completeDataAccess(pkt);
555 else
556 tickEvent.schedule(pkt, time);
557
558 return true;
559}
560
561void
562TimingSimpleCPU::DcachePort::DTickEvent::process()
563{
564 cpu->completeDataAccess(pkt);
565}
566
567void
568TimingSimpleCPU::DcachePort::recvRetry()
569{
570 // we shouldn't get a retry unless we have a packet that we're
571 // waiting to transmit
572 assert(cpu->dcache_pkt != NULL);
573 assert(cpu->_status == DcacheRetry);
574 Packet *tmp = cpu->dcache_pkt;
575 if (sendTiming(tmp)) {
576 cpu->_status = DcacheWaitResponse;
577 cpu->dcache_pkt = NULL;
578 }
579}
580
581
582////////////////////////////////////////////////////////////////////////
583//
584// TimingSimpleCPU Simulation Object
585//
586BEGIN_DECLARE_SIM_OBJECT_PARAMS(TimingSimpleCPU)
587
588 Param<Counter> max_insts_any_thread;
589 Param<Counter> max_insts_all_threads;
590 Param<Counter> max_loads_any_thread;
591 Param<Counter> max_loads_all_threads;
592 Param<Tick> progress_interval;
593 SimObjectParam<MemObject *> mem;
594 SimObjectParam<System *> system;
595
596#if FULL_SYSTEM
597 SimObjectParam<AlphaITB *> itb;
598 SimObjectParam<AlphaDTB *> dtb;
599 Param<int> cpu_id;
600 Param<Tick> profile;
601#else
602 SimObjectParam<Process *> workload;
603#endif // FULL_SYSTEM
604
605 Param<int> clock;
606
607 Param<bool> defer_registration;
608 Param<int> width;
609 Param<bool> function_trace;
610 Param<Tick> function_trace_start;
611 Param<bool> simulate_stalls;
612
613END_DECLARE_SIM_OBJECT_PARAMS(TimingSimpleCPU)
614
615BEGIN_INIT_SIM_OBJECT_PARAMS(TimingSimpleCPU)
616
617 INIT_PARAM(max_insts_any_thread,
618 "terminate when any thread reaches this inst count"),
619 INIT_PARAM(max_insts_all_threads,
620 "terminate when all threads have reached this inst count"),
621 INIT_PARAM(max_loads_any_thread,
622 "terminate when any thread reaches this load count"),
623 INIT_PARAM(max_loads_all_threads,
624 "terminate when all threads have reached this load count"),
625 INIT_PARAM(progress_interval, "Progress interval"),
626 INIT_PARAM(mem, "memory"),
627 INIT_PARAM(system, "system object"),
628
629#if FULL_SYSTEM
630 INIT_PARAM(itb, "Instruction TLB"),
631 INIT_PARAM(dtb, "Data TLB"),
632 INIT_PARAM(cpu_id, "processor ID"),
633 INIT_PARAM(profile, ""),
634#else
635 INIT_PARAM(workload, "processes to run"),
636#endif // FULL_SYSTEM
637
638 INIT_PARAM(clock, "clock speed"),
639 INIT_PARAM(defer_registration, "defer system registration (for sampling)"),
640 INIT_PARAM(width, "cpu width"),
641 INIT_PARAM(function_trace, "Enable function trace"),
642 INIT_PARAM(function_trace_start, "Cycle to start function trace"),
643 INIT_PARAM(simulate_stalls, "Simulate cache stall cycles")
644
645END_INIT_SIM_OBJECT_PARAMS(TimingSimpleCPU)
646
647
648CREATE_SIM_OBJECT(TimingSimpleCPU)
649{
650 TimingSimpleCPU::Params *params = new TimingSimpleCPU::Params();
651 params->name = getInstanceName();
652 params->numberOfThreads = 1;
653 params->max_insts_any_thread = max_insts_any_thread;
654 params->max_insts_all_threads = max_insts_all_threads;
655 params->max_loads_any_thread = max_loads_any_thread;
656 params->max_loads_all_threads = max_loads_all_threads;
657 params->progress_interval = progress_interval;
658 params->deferRegistration = defer_registration;
659 params->clock = clock;
660 params->functionTrace = function_trace;
661 params->functionTraceStart = function_trace_start;
662 params->mem = mem;
663 params->system = system;
664
665#if FULL_SYSTEM
666 params->itb = itb;
667 params->dtb = dtb;
668 params->cpu_id = cpu_id;
669 params->profile = profile;
670#else
671 params->process = workload;
672#endif
673
674 TimingSimpleCPU *cpu = new TimingSimpleCPU(params);
675 return cpu;
676}
677
678REGISTER_SIM_OBJECT("TimingSimpleCPU", TimingSimpleCPU)
679
| 336 recordEvent("Uncached Write");
337
338 // If the write needs to have a fault on the access, consider calling
339 // changeStatus() and changing it to "bad addr write" or something.
340 return fault;
341}
342
343
344#ifndef DOXYGEN_SHOULD_SKIP_THIS
345template
346Fault
347TimingSimpleCPU::write(uint64_t data, Addr addr,
348 unsigned flags, uint64_t *res);
349
350template
351Fault
352TimingSimpleCPU::write(uint32_t data, Addr addr,
353 unsigned flags, uint64_t *res);
354
355template
356Fault
357TimingSimpleCPU::write(uint16_t data, Addr addr,
358 unsigned flags, uint64_t *res);
359
360template
361Fault
362TimingSimpleCPU::write(uint8_t data, Addr addr,
363 unsigned flags, uint64_t *res);
364
365#endif //DOXYGEN_SHOULD_SKIP_THIS
366
367template<>
368Fault
369TimingSimpleCPU::write(double data, Addr addr, unsigned flags, uint64_t *res)
370{
371 return write(*(uint64_t*)&data, addr, flags, res);
372}
373
374template<>
375Fault
376TimingSimpleCPU::write(float data, Addr addr, unsigned flags, uint64_t *res)
377{
378 return write(*(uint32_t*)&data, addr, flags, res);
379}
380
381
382template<>
383Fault
384TimingSimpleCPU::write(int32_t data, Addr addr, unsigned flags, uint64_t *res)
385{
386 return write((uint32_t)data, addr, flags, res);
387}
388
389
390void
391TimingSimpleCPU::fetch()
392{
393 checkForInterrupts();
394
395 // need to fill in CPU & thread IDs here
396 Request *ifetch_req = new Request();
397 ifetch_req->setThreadContext(0,0); //Need CPU/Thread IDS HERE
398 Fault fault = setupFetchRequest(ifetch_req);
399
400 ifetch_pkt = new Packet(ifetch_req, Packet::ReadReq, Packet::Broadcast);
401 ifetch_pkt->dataStatic(&inst);
402
403 if (fault == NoFault) {
404 if (!icachePort.sendTiming(ifetch_pkt)) {
405 // Need to wait for retry
406 _status = IcacheRetry;
407 } else {
408 // Need to wait for cache to respond
409 _status = IcacheWaitResponse;
410 // ownership of packet transferred to memory system
411 ifetch_pkt = NULL;
412 }
413 } else {
414 // fetch fault: advance directly to next instruction (fault handler)
415 advanceInst(fault);
416 }
417}
418
419
420void
421TimingSimpleCPU::advanceInst(Fault fault)
422{
423 advancePC(fault);
424
425 if (_status == Running) {
426 // kick off fetch of next instruction... callback from icache
427 // response will cause that instruction to be executed,
428 // keeping the CPU running.
429 fetch();
430 }
431}
432
433
434void
435TimingSimpleCPU::completeIfetch(Packet *pkt)
436{
437 // received a response from the icache: execute the received
438 // instruction
439 assert(pkt->result == Packet::Success);
440 assert(_status == IcacheWaitResponse);
441
442 _status = Running;
443
444 delete pkt->req;
445 delete pkt;
446
447 if (getState() == SimObject::Draining) {
448 completeDrain();
449 return;
450 }
451
452 preExecute();
453 if (curStaticInst->isMemRef() && !curStaticInst->isDataPrefetch()) {
454 // load or store: just send to dcache
455 Fault fault = curStaticInst->initiateAcc(this, traceData);
456 if (fault == NoFault) {
457 // successfully initiated access: instruction will
458 // complete in dcache response callback
459 assert(_status == DcacheWaitResponse);
460 } else {
461 // fault: complete now to invoke fault handler
462 postExecute();
463 advanceInst(fault);
464 }
465 } else {
466 // non-memory instruction: execute completely now
467 Fault fault = curStaticInst->execute(this, traceData);
468 postExecute();
469 advanceInst(fault);
470 }
471}
472
473void
474TimingSimpleCPU::IcachePort::ITickEvent::process()
475{
476 cpu->completeIfetch(pkt);
477}
478
479bool
480TimingSimpleCPU::IcachePort::recvTiming(Packet *pkt)
481{
482 // These next few lines could be replaced with something faster
483 // who knows what though
484 Tick time = pkt->req->getTime();
485 while (time < curTick)
486 time += lat;
487
488 if (time == curTick)
489 cpu->completeIfetch(pkt);
490 else
491 tickEvent.schedule(pkt, time);
492
493 return true;
494}
495
496void
497TimingSimpleCPU::IcachePort::recvRetry()
498{
499 // we shouldn't get a retry unless we have a packet that we're
500 // waiting to transmit
501 assert(cpu->ifetch_pkt != NULL);
502 assert(cpu->_status == IcacheRetry);
503 Packet *tmp = cpu->ifetch_pkt;
504 if (sendTiming(tmp)) {
505 cpu->_status = IcacheWaitResponse;
506 cpu->ifetch_pkt = NULL;
507 }
508}
509
510void
511TimingSimpleCPU::completeDataAccess(Packet *pkt)
512{
513 // received a response from the dcache: complete the load or store
514 // instruction
515 assert(pkt->result == Packet::Success);
516 assert(_status == DcacheWaitResponse);
517 _status = Running;
518
519 if (getState() == SimObject::Draining) {
520 completeDrain();
521
522 delete pkt->req;
523 delete pkt;
524
525 return;
526 }
527
528 Fault fault = curStaticInst->completeAcc(pkt, this, traceData);
529
530 delete pkt->req;
531 delete pkt;
532
533 postExecute();
534 advanceInst(fault);
535}
536
537
538void
539TimingSimpleCPU::completeDrain()
540{
541 DPRINTF(Config, "Done draining\n");
542 changeState(SimObject::Drained);
543 drainEvent->process();
544}
545
546bool
547TimingSimpleCPU::DcachePort::recvTiming(Packet *pkt)
548{
549 Tick time = pkt->req->getTime();
550 while (time < curTick)
551 time += lat;
552
553 if (time == curTick)
554 cpu->completeDataAccess(pkt);
555 else
556 tickEvent.schedule(pkt, time);
557
558 return true;
559}
560
561void
562TimingSimpleCPU::DcachePort::DTickEvent::process()
563{
564 cpu->completeDataAccess(pkt);
565}
566
567void
568TimingSimpleCPU::DcachePort::recvRetry()
569{
570 // we shouldn't get a retry unless we have a packet that we're
571 // waiting to transmit
572 assert(cpu->dcache_pkt != NULL);
573 assert(cpu->_status == DcacheRetry);
574 Packet *tmp = cpu->dcache_pkt;
575 if (sendTiming(tmp)) {
576 cpu->_status = DcacheWaitResponse;
577 cpu->dcache_pkt = NULL;
578 }
579}
580
581
582////////////////////////////////////////////////////////////////////////
583//
584// TimingSimpleCPU Simulation Object
585//
586BEGIN_DECLARE_SIM_OBJECT_PARAMS(TimingSimpleCPU)
587
588 Param<Counter> max_insts_any_thread;
589 Param<Counter> max_insts_all_threads;
590 Param<Counter> max_loads_any_thread;
591 Param<Counter> max_loads_all_threads;
592 Param<Tick> progress_interval;
593 SimObjectParam<MemObject *> mem;
594 SimObjectParam<System *> system;
595
596#if FULL_SYSTEM
597 SimObjectParam<AlphaITB *> itb;
598 SimObjectParam<AlphaDTB *> dtb;
599 Param<int> cpu_id;
600 Param<Tick> profile;
601#else
602 SimObjectParam<Process *> workload;
603#endif // FULL_SYSTEM
604
605 Param<int> clock;
606
607 Param<bool> defer_registration;
608 Param<int> width;
609 Param<bool> function_trace;
610 Param<Tick> function_trace_start;
611 Param<bool> simulate_stalls;
612
613END_DECLARE_SIM_OBJECT_PARAMS(TimingSimpleCPU)
614
615BEGIN_INIT_SIM_OBJECT_PARAMS(TimingSimpleCPU)
616
617 INIT_PARAM(max_insts_any_thread,
618 "terminate when any thread reaches this inst count"),
619 INIT_PARAM(max_insts_all_threads,
620 "terminate when all threads have reached this inst count"),
621 INIT_PARAM(max_loads_any_thread,
622 "terminate when any thread reaches this load count"),
623 INIT_PARAM(max_loads_all_threads,
624 "terminate when all threads have reached this load count"),
625 INIT_PARAM(progress_interval, "Progress interval"),
626 INIT_PARAM(mem, "memory"),
627 INIT_PARAM(system, "system object"),
628
629#if FULL_SYSTEM
630 INIT_PARAM(itb, "Instruction TLB"),
631 INIT_PARAM(dtb, "Data TLB"),
632 INIT_PARAM(cpu_id, "processor ID"),
633 INIT_PARAM(profile, ""),
634#else
635 INIT_PARAM(workload, "processes to run"),
636#endif // FULL_SYSTEM
637
638 INIT_PARAM(clock, "clock speed"),
639 INIT_PARAM(defer_registration, "defer system registration (for sampling)"),
640 INIT_PARAM(width, "cpu width"),
641 INIT_PARAM(function_trace, "Enable function trace"),
642 INIT_PARAM(function_trace_start, "Cycle to start function trace"),
643 INIT_PARAM(simulate_stalls, "Simulate cache stall cycles")
644
645END_INIT_SIM_OBJECT_PARAMS(TimingSimpleCPU)
646
647
648CREATE_SIM_OBJECT(TimingSimpleCPU)
649{
650 TimingSimpleCPU::Params *params = new TimingSimpleCPU::Params();
651 params->name = getInstanceName();
652 params->numberOfThreads = 1;
653 params->max_insts_any_thread = max_insts_any_thread;
654 params->max_insts_all_threads = max_insts_all_threads;
655 params->max_loads_any_thread = max_loads_any_thread;
656 params->max_loads_all_threads = max_loads_all_threads;
657 params->progress_interval = progress_interval;
658 params->deferRegistration = defer_registration;
659 params->clock = clock;
660 params->functionTrace = function_trace;
661 params->functionTraceStart = function_trace_start;
662 params->mem = mem;
663 params->system = system;
664
665#if FULL_SYSTEM
666 params->itb = itb;
667 params->dtb = dtb;
668 params->cpu_id = cpu_id;
669 params->profile = profile;
670#else
671 params->process = workload;
672#endif
673
674 TimingSimpleCPU *cpu = new TimingSimpleCPU(params);
675 return cpu;
676}
677
678REGISTER_SIM_OBJECT("TimingSimpleCPU", TimingSimpleCPU)
679
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