timing.cc (8832:247fee427324) | timing.cc (8850:ed91b534ed04) |
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1/* 2 * Copyright (c) 2010 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 46 unchanged lines hidden (view full) --- 55#include "params/TimingSimpleCPU.hh" 56#include "sim/faults.hh" 57#include "sim/full_system.hh" 58#include "sim/system.hh" 59 60using namespace std; 61using namespace TheISA; 62 | 1/* 2 * Copyright (c) 2010 ARM Limited 3 * All rights reserved 4 * 5 * The license below extends only to copyright in the software and shall 6 * not be construed as granting a license to any other intellectual 7 * property including but not limited to intellectual property relating 8 * to a hardware implementation of the functionality of the software --- 46 unchanged lines hidden (view full) --- 55#include "params/TimingSimpleCPU.hh" 56#include "sim/faults.hh" 57#include "sim/full_system.hh" 58#include "sim/system.hh" 59 60using namespace std; 61using namespace TheISA; 62 |
63Port * 64TimingSimpleCPU::getPort(const std::string &if_name, int idx) 65{ 66 if (if_name == "dcache_port") 67 return &dcachePort; 68 else if (if_name == "icache_port") 69 return &icachePort; 70 else 71 panic("No Such Port\n"); 72} 73 | |
74void 75TimingSimpleCPU::init() 76{ 77 BaseCPU::init(); 78 if (FullSystem) { 79 for (int i = 0; i < threadContexts.size(); ++i) { 80 ThreadContext *tc = threadContexts[i]; 81 // initialize CPU, including PC --- 891 unchanged lines hidden --- | 63void 64TimingSimpleCPU::init() 65{ 66 BaseCPU::init(); 67 if (FullSystem) { 68 for (int i = 0; i < threadContexts.size(); ++i) { 69 ThreadContext *tc = threadContexts[i]; 70 // initialize CPU, including PC --- 891 unchanged lines hidden --- |