timing.cc (5710:b44dd45bd604) | timing.cc (5712:199d31b47f7b) |
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1/* 2 * Copyright (c) 2002-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 43 unchanged lines hidden (view full) --- 52 else 53 panic("No Such Port\n"); 54} 55 56void 57TimingSimpleCPU::init() 58{ 59 BaseCPU::init(); | 1/* 2 * Copyright (c) 2002-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 43 unchanged lines hidden (view full) --- 52 else 53 panic("No Such Port\n"); 54} 55 56void 57TimingSimpleCPU::init() 58{ 59 BaseCPU::init(); |
60 cpuId = tc->readCpuId(); | |
61#if FULL_SYSTEM 62 for (int i = 0; i < threadContexts.size(); ++i) { 63 ThreadContext *tc = threadContexts[i]; 64 65 // initialize CPU, including PC | 60#if FULL_SYSTEM 61 for (int i = 0; i < threadContexts.size(); ++i) { 62 ThreadContext *tc = threadContexts[i]; 63 64 // initialize CPU, including PC |
66 TheISA::initCPU(tc, cpuId); | 65 TheISA::initCPU(tc, _cpuId); |
67 } 68#endif 69} 70 71Tick 72TimingSimpleCPU::CpuPort::recvAtomic(PacketPtr pkt) 73{ 74 panic("TimingSimpleCPU doesn't expect recvAtomic callback!"); --- 123 unchanged lines hidden (view full) --- 198 break; 199 } 200 } 201 202 if (_status != Running) { 203 _status = Idle; 204 } 205 assert(threadContexts.size() == 1); | 66 } 67#endif 68} 69 70Tick 71TimingSimpleCPU::CpuPort::recvAtomic(PacketPtr pkt) 72{ 73 panic("TimingSimpleCPU doesn't expect recvAtomic callback!"); --- 123 unchanged lines hidden (view full) --- 197 break; 198 } 199 } 200 201 if (_status != Running) { 202 _status = Idle; 203 } 204 assert(threadContexts.size() == 1); |
206 cpuId = tc->readCpuId(); | 205 _cpuId = tc->cpuId(); |
207 previousTick = curTick; 208} 209 210 211void 212TimingSimpleCPU::activateContext(int thread_num, int delay) 213{ 214 DPRINTF(SimpleCPU, "ActivateContext %d (%d cycles)\n", thread_num, delay); --- 30 unchanged lines hidden (view full) --- 245 246 247template <class T> 248Fault 249TimingSimpleCPU::read(Addr addr, T &data, unsigned flags) 250{ 251 Request *req = 252 new Request(/* asid */ 0, addr, sizeof(T), flags, thread->readPC(), | 206 previousTick = curTick; 207} 208 209 210void 211TimingSimpleCPU::activateContext(int thread_num, int delay) 212{ 213 DPRINTF(SimpleCPU, "ActivateContext %d (%d cycles)\n", thread_num, delay); --- 30 unchanged lines hidden (view full) --- 244 245 246template <class T> 247Fault 248TimingSimpleCPU::read(Addr addr, T &data, unsigned flags) 249{ 250 Request *req = 251 new Request(/* asid */ 0, addr, sizeof(T), flags, thread->readPC(), |
253 cpuId, /* thread ID */ 0); | 252 _cpuId, /* thread ID */ 0); |
254 255 if (traceData) { 256 traceData->setAddr(req->getVaddr()); 257 } 258 259 // translate to physical address 260 Fault fault = thread->translateDataReadReq(req); 261 --- 34 unchanged lines hidden (view full) --- 296 return fault; 297} 298 299Fault 300TimingSimpleCPU::translateDataReadAddr(Addr vaddr, Addr &paddr, 301 int size, unsigned flags) 302{ 303 Request *req = | 253 254 if (traceData) { 255 traceData->setAddr(req->getVaddr()); 256 } 257 258 // translate to physical address 259 Fault fault = thread->translateDataReadReq(req); 260 --- 34 unchanged lines hidden (view full) --- 295 return fault; 296} 297 298Fault 299TimingSimpleCPU::translateDataReadAddr(Addr vaddr, Addr &paddr, 300 int size, unsigned flags) 301{ 302 Request *req = |
304 new Request(0, vaddr, size, flags, thread->readPC(), cpuId, 0); | 303 new Request(0, vaddr, size, flags, thread->readPC(), _cpuId, 0); |
305 306 if (traceData) { 307 traceData->setAddr(vaddr); 308 } 309 310 Fault fault = thread->translateDataWriteReq(req); 311 312 if (fault == NoFault) --- 55 unchanged lines hidden (view full) --- 368 369 370template <class T> 371Fault 372TimingSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res) 373{ 374 Request *req = 375 new Request(/* asid */ 0, addr, sizeof(T), flags, thread->readPC(), | 304 305 if (traceData) { 306 traceData->setAddr(vaddr); 307 } 308 309 Fault fault = thread->translateDataWriteReq(req); 310 311 if (fault == NoFault) --- 55 unchanged lines hidden (view full) --- 367 368 369template <class T> 370Fault 371TimingSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res) 372{ 373 Request *req = 374 new Request(/* asid */ 0, addr, sizeof(T), flags, thread->readPC(), |
376 cpuId, /* thread ID */ 0); | 375 _cpuId, /* thread ID */ 0); |
377 378 if (traceData) { 379 traceData->setAddr(req->getVaddr()); 380 } 381 382 // translate to physical address 383 Fault fault = thread->translateDataWriteReq(req); 384 --- 52 unchanged lines hidden (view full) --- 437 return fault; 438} 439 440Fault 441TimingSimpleCPU::translateDataWriteAddr(Addr vaddr, Addr &paddr, 442 int size, unsigned flags) 443{ 444 Request *req = | 376 377 if (traceData) { 378 traceData->setAddr(req->getVaddr()); 379 } 380 381 // translate to physical address 382 Fault fault = thread->translateDataWriteReq(req); 383 --- 52 unchanged lines hidden (view full) --- 436 return fault; 437} 438 439Fault 440TimingSimpleCPU::translateDataWriteAddr(Addr vaddr, Addr &paddr, 441 int size, unsigned flags) 442{ 443 Request *req = |
445 new Request(0, vaddr, size, flags, thread->readPC(), cpuId, 0); | 444 new Request(0, vaddr, size, flags, thread->readPC(), _cpuId, 0); |
446 447 if (traceData) { 448 traceData->setAddr(vaddr); 449 } 450 451 Fault fault = thread->translateDataWriteReq(req); 452 453 if (fault == NoFault) --- 69 unchanged lines hidden (view full) --- 523 checkForInterrupts(); 524 525 checkPcEventQueue(); 526 527 bool fromRom = isRomMicroPC(thread->readMicroPC()); 528 529 if (!fromRom) { 530 Request *ifetch_req = new Request(); | 445 446 if (traceData) { 447 traceData->setAddr(vaddr); 448 } 449 450 Fault fault = thread->translateDataWriteReq(req); 451 452 if (fault == NoFault) --- 69 unchanged lines hidden (view full) --- 522 checkForInterrupts(); 523 524 checkPcEventQueue(); 525 526 bool fromRom = isRomMicroPC(thread->readMicroPC()); 527 528 if (!fromRom) { 529 Request *ifetch_req = new Request(); |
531 ifetch_req->setThreadContext(cpuId, /* thread ID */ 0); | 530 ifetch_req->setThreadContext(_cpuId, /* thread ID */ 0); |
532 Fault fault = setupFetchRequest(ifetch_req); 533 534 ifetch_pkt = new Packet(ifetch_req, MemCmd::ReadReq, Packet::Broadcast); 535 ifetch_pkt->dataStatic(&inst); 536 537 if (fault == NoFault) { 538 if (!icachePort.sendTiming(ifetch_pkt)) { 539 // Need to wait for retry --- 329 unchanged lines hidden --- | 531 Fault fault = setupFetchRequest(ifetch_req); 532 533 ifetch_pkt = new Packet(ifetch_req, MemCmd::ReadReq, Packet::Broadcast); 534 ifetch_pkt->dataStatic(&inst); 535 536 if (fault == NoFault) { 537 if (!icachePort.sendTiming(ifetch_pkt)) { 538 // Need to wait for retry --- 329 unchanged lines hidden --- |