timing.cc (2901:f9a45473ab55) | timing.cc (2915:1f4d02556ac1) |
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1/* 2 * Copyright (c) 2002-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 19 unchanged lines hidden (view full) --- 28 * Authors: Steve Reinhardt 29 */ 30 31#include "arch/utility.hh" 32#include "cpu/exetrace.hh" 33#include "cpu/simple/timing.hh" 34#include "mem/packet_impl.hh" 35#include "sim/builder.hh" | 1/* 2 * Copyright (c) 2002-2005 The Regents of The University of Michigan 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions are 7 * met: redistributions of source code must retain the above copyright 8 * notice, this list of conditions and the following disclaimer; --- 19 unchanged lines hidden (view full) --- 28 * Authors: Steve Reinhardt 29 */ 30 31#include "arch/utility.hh" 32#include "cpu/exetrace.hh" 33#include "cpu/simple/timing.hh" 34#include "mem/packet_impl.hh" 35#include "sim/builder.hh" |
36#include "sim/system.hh" | |
37 38using namespace std; 39using namespace TheISA; 40 41Port * 42TimingSimpleCPU::getPort(const std::string &if_name, int idx) 43{ 44 if (if_name == "dcache_port") --- 42 unchanged lines hidden (view full) --- 87 88TimingSimpleCPU::TimingSimpleCPU(Params *p) 89 : BaseSimpleCPU(p), icachePort(this), dcachePort(this) 90{ 91 _status = Idle; 92 ifetch_pkt = dcache_pkt = NULL; 93 drainEvent = NULL; 94 fetchEvent = NULL; | 36 37using namespace std; 38using namespace TheISA; 39 40Port * 41TimingSimpleCPU::getPort(const std::string &if_name, int idx) 42{ 43 if (if_name == "dcache_port") --- 42 unchanged lines hidden (view full) --- 86 87TimingSimpleCPU::TimingSimpleCPU(Params *p) 88 : BaseSimpleCPU(p), icachePort(this), dcachePort(this) 89{ 90 _status = Idle; 91 ifetch_pkt = dcache_pkt = NULL; 92 drainEvent = NULL; 93 fetchEvent = NULL; |
95 changeState(SimObject::Running); | 94 state = SimObject::Timing; |
96} 97 98 99TimingSimpleCPU::~TimingSimpleCPU() 100{ 101} 102 103void 104TimingSimpleCPU::serialize(ostream &os) 105{ | 95} 96 97 98TimingSimpleCPU::~TimingSimpleCPU() 99{ 100} 101 102void 103TimingSimpleCPU::serialize(ostream &os) 104{ |
106 SERIALIZE_ENUM(_status); | 105 SimObject::State so_state = SimObject::getState(); 106 SERIALIZE_ENUM(so_state); |
107 BaseSimpleCPU::serialize(os); 108} 109 110void 111TimingSimpleCPU::unserialize(Checkpoint *cp, const string §ion) 112{ | 107 BaseSimpleCPU::serialize(os); 108} 109 110void 111TimingSimpleCPU::unserialize(Checkpoint *cp, const string §ion) 112{ |
113 UNSERIALIZE_ENUM(_status); | 113 SimObject::State so_state; 114 UNSERIALIZE_ENUM(so_state); |
114 BaseSimpleCPU::unserialize(cp, section); 115} 116 | 115 BaseSimpleCPU::unserialize(cp, section); 116} 117 |
117unsigned int | 118bool |
118TimingSimpleCPU::drain(Event *drain_event) 119{ 120 // TimingSimpleCPU is ready to drain if it's not waiting for 121 // an access to complete. 122 if (status() == Idle || status() == Running || status() == SwitchedOut) { | 119TimingSimpleCPU::drain(Event *drain_event) 120{ 121 // TimingSimpleCPU is ready to drain if it's not waiting for 122 // an access to complete. 123 if (status() == Idle || status() == Running || status() == SwitchedOut) { |
123 changeState(SimObject::Drained); 124 return 0; | 124 changeState(SimObject::DrainedTiming); 125 return true; |
125 } else { 126 changeState(SimObject::Draining); 127 drainEvent = drain_event; | 126 } else { 127 changeState(SimObject::Draining); 128 drainEvent = drain_event; |
128 return 1; | 129 return false; |
129 } 130} 131 132void 133TimingSimpleCPU::resume() 134{ 135 if (_status != SwitchedOut && _status != Idle) { 136 // Delete the old event if it existed. 137 if (fetchEvent) { | 130 } 131} 132 133void 134TimingSimpleCPU::resume() 135{ 136 if (_status != SwitchedOut && _status != Idle) { 137 // Delete the old event if it existed. 138 if (fetchEvent) { |
138 assert(!fetchEvent->scheduled()); | 139 if (fetchEvent->scheduled()) 140 fetchEvent->deschedule(); 141 |
139 delete fetchEvent; 140 } 141 142 fetchEvent = 143 new EventWrapper<TimingSimpleCPU, &TimingSimpleCPU::fetch>(this, false); 144 fetchEvent->schedule(curTick); 145 } | 142 delete fetchEvent; 143 } 144 145 fetchEvent = 146 new EventWrapper<TimingSimpleCPU, &TimingSimpleCPU::fetch>(this, false); 147 fetchEvent->schedule(curTick); 148 } |
149} |
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146 | 150 |
147 assert(system->getMemoryMode() == System::Timing); 148 changeState(SimObject::Running); | 151void 152TimingSimpleCPU::setMemoryMode(State new_mode) 153{ 154 assert(new_mode == SimObject::Timing); |
149} 150 151void 152TimingSimpleCPU::switchOut() 153{ 154 assert(status() == Running || status() == Idle); 155 _status = SwitchedOut; 156 --- 350 unchanged lines hidden (view full) --- 507 advanceInst(fault); 508} 509 510 511void 512TimingSimpleCPU::completeDrain() 513{ 514 DPRINTF(Config, "Done draining\n"); | 155} 156 157void 158TimingSimpleCPU::switchOut() 159{ 160 assert(status() == Running || status() == Idle); 161 _status = SwitchedOut; 162 --- 350 unchanged lines hidden (view full) --- 513 advanceInst(fault); 514} 515 516 517void 518TimingSimpleCPU::completeDrain() 519{ 520 DPRINTF(Config, "Done draining\n"); |
515 changeState(SimObject::Drained); | 521 changeState(SimObject::DrainedTiming); |
516 drainEvent->process(); 517} 518 519bool 520TimingSimpleCPU::DcachePort::recvTiming(Packet *pkt) 521{ 522 cpu->completeDataAccess(pkt); 523 return true; --- 20 unchanged lines hidden (view full) --- 544// 545BEGIN_DECLARE_SIM_OBJECT_PARAMS(TimingSimpleCPU) 546 547 Param<Counter> max_insts_any_thread; 548 Param<Counter> max_insts_all_threads; 549 Param<Counter> max_loads_any_thread; 550 Param<Counter> max_loads_all_threads; 551 SimObjectParam<MemObject *> mem; | 522 drainEvent->process(); 523} 524 525bool 526TimingSimpleCPU::DcachePort::recvTiming(Packet *pkt) 527{ 528 cpu->completeDataAccess(pkt); 529 return true; --- 20 unchanged lines hidden (view full) --- 550// 551BEGIN_DECLARE_SIM_OBJECT_PARAMS(TimingSimpleCPU) 552 553 Param<Counter> max_insts_any_thread; 554 Param<Counter> max_insts_all_threads; 555 Param<Counter> max_loads_any_thread; 556 Param<Counter> max_loads_all_threads; 557 SimObjectParam<MemObject *> mem; |
552 SimObjectParam<System *> system; | |
553 554#if FULL_SYSTEM 555 SimObjectParam<AlphaITB *> itb; 556 SimObjectParam<AlphaDTB *> dtb; | 558 559#if FULL_SYSTEM 560 SimObjectParam<AlphaITB *> itb; 561 SimObjectParam<AlphaDTB *> dtb; |
562 SimObjectParam<System *> system; |
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557 Param<int> cpu_id; 558 Param<Tick> profile; 559#else 560 SimObjectParam<Process *> workload; 561#endif // FULL_SYSTEM 562 563 Param<int> clock; 564 --- 11 unchanged lines hidden (view full) --- 576 "terminate when any thread reaches this inst count"), 577 INIT_PARAM(max_insts_all_threads, 578 "terminate when all threads have reached this inst count"), 579 INIT_PARAM(max_loads_any_thread, 580 "terminate when any thread reaches this load count"), 581 INIT_PARAM(max_loads_all_threads, 582 "terminate when all threads have reached this load count"), 583 INIT_PARAM(mem, "memory"), | 563 Param<int> cpu_id; 564 Param<Tick> profile; 565#else 566 SimObjectParam<Process *> workload; 567#endif // FULL_SYSTEM 568 569 Param<int> clock; 570 --- 11 unchanged lines hidden (view full) --- 582 "terminate when any thread reaches this inst count"), 583 INIT_PARAM(max_insts_all_threads, 584 "terminate when all threads have reached this inst count"), 585 INIT_PARAM(max_loads_any_thread, 586 "terminate when any thread reaches this load count"), 587 INIT_PARAM(max_loads_all_threads, 588 "terminate when all threads have reached this load count"), 589 INIT_PARAM(mem, "memory"), |
584 INIT_PARAM(system, "system object"), | |
585 586#if FULL_SYSTEM 587 INIT_PARAM(itb, "Instruction TLB"), 588 INIT_PARAM(dtb, "Data TLB"), | 590 591#if FULL_SYSTEM 592 INIT_PARAM(itb, "Instruction TLB"), 593 INIT_PARAM(dtb, "Data TLB"), |
594 INIT_PARAM(system, "system object"), |
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589 INIT_PARAM(cpu_id, "processor ID"), 590 INIT_PARAM(profile, ""), 591#else 592 INIT_PARAM(workload, "processes to run"), 593#endif // FULL_SYSTEM 594 595 INIT_PARAM(clock, "clock speed"), 596 INIT_PARAM(defer_registration, "defer system registration (for sampling)"), --- 14 unchanged lines hidden (view full) --- 611 params->max_insts_all_threads = max_insts_all_threads; 612 params->max_loads_any_thread = max_loads_any_thread; 613 params->max_loads_all_threads = max_loads_all_threads; 614 params->deferRegistration = defer_registration; 615 params->clock = clock; 616 params->functionTrace = function_trace; 617 params->functionTraceStart = function_trace_start; 618 params->mem = mem; | 595 INIT_PARAM(cpu_id, "processor ID"), 596 INIT_PARAM(profile, ""), 597#else 598 INIT_PARAM(workload, "processes to run"), 599#endif // FULL_SYSTEM 600 601 INIT_PARAM(clock, "clock speed"), 602 INIT_PARAM(defer_registration, "defer system registration (for sampling)"), --- 14 unchanged lines hidden (view full) --- 617 params->max_insts_all_threads = max_insts_all_threads; 618 params->max_loads_any_thread = max_loads_any_thread; 619 params->max_loads_all_threads = max_loads_all_threads; 620 params->deferRegistration = defer_registration; 621 params->clock = clock; 622 params->functionTrace = function_trace; 623 params->functionTraceStart = function_trace_start; 624 params->mem = mem; |
619 params->system = system; | |
620 621#if FULL_SYSTEM 622 params->itb = itb; 623 params->dtb = dtb; | 625 626#if FULL_SYSTEM 627 params->itb = itb; 628 params->dtb = dtb; |
629 params->system = system; |
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624 params->cpu_id = cpu_id; 625 params->profile = profile; 626#else 627 params->process = workload; 628#endif 629 630 TimingSimpleCPU *cpu = new TimingSimpleCPU(params); 631 return cpu; 632} 633 634REGISTER_SIM_OBJECT("TimingSimpleCPU", TimingSimpleCPU) 635 | 630 params->cpu_id = cpu_id; 631 params->profile = profile; 632#else 633 params->process = workload; 634#endif 635 636 TimingSimpleCPU *cpu = new TimingSimpleCPU(params); 637 return cpu; 638} 639 640REGISTER_SIM_OBJECT("TimingSimpleCPU", TimingSimpleCPU) 641 |