1/*
2 * Copyright (c) 2010-2012 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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138
139 assert(!threadContexts.empty());
140 if (threadContexts.size() > 1)
141 fatal("The timing CPU only supports one thread.\n");
142
143 if (thread->status() == ThreadContext::Active) {
144 schedule(fetchEvent, nextCycle());
145 _status = BaseSimpleCPU::Running;
146 } else {
147 _status = BaseSimpleCPU::Idle;
148 }
149}
150
151bool
152TimingSimpleCPU::tryCompleteDrain()
153{
154 if (!drainManager)
155 return false;

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201{
202 DPRINTF(SimpleCPU, "ActivateContext %d (%d cycles)\n", thread_num, delay);
203
204 assert(thread_num == 0);
205 assert(thread);
206
207 assert(_status == Idle);
208
209 notIdleFraction++;
210 _status = BaseSimpleCPU::Running;
211
212 // kick things off by initiating the fetch of the next instruction
213 schedule(fetchEvent, clockEdge(delay));
214}
215
216
217void

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225 if (_status == Idle)
226 return;
227
228 assert(_status == BaseSimpleCPU::Running);
229
230 // just change status to Idle... if status != Running,
231 // completeInst() will not initiate fetch of next instruction.
232
233 notIdleFraction--;
234 _status = Idle;
235}
236
237bool
238TimingSimpleCPU::handleReadPacket(PacketPtr pkt)
239{
240 RequestPtr req = pkt->req;
241 if (req->isMmappedIpr()) {

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