1/*
2 * Copyright (c) 2010-2012 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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104
105TimingSimpleCPU::~TimingSimpleCPU()
106{
107}
108
109unsigned int
110TimingSimpleCPU::drain(DrainManager *drain_manager)
111{
112 if (_status == Idle ||
113 (_status == BaseSimpleCPU::Running && isDrained()) ||
114 _status == SwitchedOut) {
115 assert(!fetchEvent.scheduled());
116 DPRINTF(Drain, "No need to drain.\n");
117 return 0;
118 } else {
119 drainManager = drain_manager;
120 DPRINTF(Drain, "Requesting drain: %s\n", pcState());
121
122 // The fetch event can become descheduled if a drain didn't
123 // succeed on the first attempt. We need to reschedule it if
124 // the CPU is waiting for a microcode routine to complete.
125 if (_status == BaseSimpleCPU::Running && !isDrained() &&
126 !fetchEvent.scheduled()) {
127 schedule(fetchEvent, nextCycle());
128 }
129
130 return 1;
131 }
132}
133
134void
135TimingSimpleCPU::drainResume()
136{
137 assert(!fetchEvent.scheduled());
138
139 DPRINTF(SimpleCPU, "Resume\n");
140 if (_status != SwitchedOut && _status != Idle) {
141 if (system->getMemoryMode() != Enums::timing) {
142 fatal("The timing CPU requires the memory system to be in "
143 "'timing' mode.\n");
144 }
145
146 schedule(fetchEvent, nextCycle());
147 }
148}
149
150bool
151TimingSimpleCPU::tryCompleteDrain()
152{
153 if (!drainManager)
154 return false;

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169{
170 BaseSimpleCPU::switchOut();
171
172 assert(!fetchEvent.scheduled());
173 assert(_status == BaseSimpleCPU::Running || _status == Idle);
174 assert(!stayAtPC);
175 assert(microPC() == 0);
176
177 _status = SwitchedOut;
178 numCycles += curCycle() - previousCycle;
179}
180
181
182void
183TimingSimpleCPU::takeOverFrom(BaseCPU *oldCPU)
184{
185 BaseSimpleCPU::takeOverFrom(oldCPU);
186
187 // if any of this CPU's ThreadContexts are active, mark the CPU as
188 // running and schedule its tick event.
189 for (int i = 0; i < threadContexts.size(); ++i) {
190 ThreadContext *tc = threadContexts[i];
191 if (tc->status() == ThreadContext::Active &&
192 _status != BaseSimpleCPU::Running) {
193 _status = BaseSimpleCPU::Running;
194 break;
195 }
196 }
197
198 if (_status != BaseSimpleCPU::Running) {
199 _status = Idle;
200 }
201 assert(threadContexts.size() == 1);
202 previousCycle = curCycle();
203}
204
205
206void
207TimingSimpleCPU::activateContext(ThreadID thread_num, Cycles delay)
208{
209 DPRINTF(SimpleCPU, "ActivateContext %d (%d cycles)\n", thread_num, delay);

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