1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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49#include "cpu/exetrace.hh"
50#include "debug/Config.hh"
51#include "debug/ExecFaulting.hh"
52#include "debug/SimpleCPU.hh"
53#include "mem/packet.hh"
54#include "mem/packet_access.hh"
55#include "params/TimingSimpleCPU.hh"
56#include "sim/faults.hh"
57#include "sim/system.hh"
58
59using namespace std;
60using namespace TheISA;
61
62Port *
63TimingSimpleCPU::getPort(const std::string &if_name, int idx)
64{

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69 else
70 panic("No Such Port\n");
71}
72
73void
74TimingSimpleCPU::init()
75{
76 BaseCPU::init();
77#if FULL_SYSTEM
78 for (int i = 0; i < threadContexts.size(); ++i) {
79 ThreadContext *tc = threadContexts[i];
80
81 // initialize CPU, including PC
82 TheISA::initCPU(tc, _cpuId);
83 }
84
85 // Initialise the ThreadContext's memory proxies
86 tcBase()->initMemProxies(tcBase());
87#endif
88}
89
90void
91TimingSimpleCPU::TimingCPUPort::TickEvent::schedule(PacketPtr _pkt, Tick t)
92{
93 pkt = _pkt;
94 cpu->schedule(this, t);
95}
96
97TimingSimpleCPU::TimingSimpleCPU(TimingSimpleCPUParams *p)
98 : BaseSimpleCPU(p), fetchTranslation(this), icachePort(this),
99 dcachePort(this), fetchEvent(this)
100{
101 _status = Idle;
102
103 ifetch_pkt = dcache_pkt = NULL;
104 drainEvent = NULL;
105 previousTick = 0;
106 changeState(SimObject::Running);
107 system->totalNumInsts = 0;
108}
109
110

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171 if (fetchEvent.scheduled())
172 deschedule(fetchEvent);
173}
174
175
176void
177TimingSimpleCPU::takeOverFrom(BaseCPU *oldCPU)
178{
179 BaseCPU::takeOverFrom(oldCPU);
180
181 // if any of this CPU's ThreadContexts are active, mark the CPU as
182 // running and schedule its tick event.
183 for (int i = 0; i < threadContexts.size(); ++i) {
184 ThreadContext *tc = threadContexts[i];
185 if (tc->status() == ThreadContext::Active && _status != Running) {
186 _status = Running;
187 break;

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192 _status = Idle;
193 }
194 assert(threadContexts.size() == 1);
195 previousTick = curTick();
196}
197
198
199void
200TimingSimpleCPU::activateContext(ThreadID thread_num, int delay)
201{
202 DPRINTF(SimpleCPU, "ActivateContext %d (%d cycles)\n", thread_num, delay);
203
204 assert(thread_num == 0);
205 assert(thread);
206
207 assert(_status == Idle);
208
209 notIdleFraction++;
210 _status = Running;
211
212 // kick things off by initiating the fetch of the next instruction
213 schedule(fetchEvent, nextCycle(curTick() + ticks(delay)));
214}
215
216
217void
218TimingSimpleCPU::suspendContext(ThreadID thread_num)
219{
220 DPRINTF(SimpleCPU, "SuspendContext %d\n", thread_num);
221
222 assert(thread_num == 0);
223 assert(thread);
224
225 if (_status == Idle)
226 return;

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840void
841TimingSimpleCPU::completeDrain()
842{
843 DPRINTF(Config, "Done draining\n");
844 changeState(SimObject::Drained);
845 drainEvent->process();
846}
847
848bool
849TimingSimpleCPU::DcachePort::recvTiming(PacketPtr pkt)
850{
851 if (pkt->isResponse() && !pkt->wasNacked()) {
852 // delay processing of returned data until next CPU clock edge
853 Tick next_tick = cpu->nextCycle(curTick());
854
855 if (next_tick == curTick()) {
856 cpu->completeDataAccess(pkt);
857 } else {
858 if (!tickEvent.scheduled()) {
859 tickEvent.schedule(pkt, next_tick);
860 } else {
861 // In the case of a split transaction and a cache that is
862 // faster than a CPU we could get two responses before
863 // next_tick expires
864 if (!retryEvent.scheduled())
865 cpu->schedule(retryEvent, next_tick);
866 return false;
867 }
868 }
869
870 return true;
871 }
872 else if (pkt->wasNacked()) {
873 assert(cpu->_status == DcacheWaitResponse);

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962//
963// TimingSimpleCPU Simulation Object
964//
965TimingSimpleCPU *
966TimingSimpleCPUParams::create()
967{
968 numThreads = 1;
969#if !FULL_SYSTEM
970 if (workload.size() != 1)
971 panic("only one workload allowed");
972#endif
973 return new TimingSimpleCPU(this);
974}