1/*
2 * Copyright (c) 2010 ARM Limited
3 * All rights reserved
4 *
5 * The license below extends only to copyright in the software and shall
6 * not be construed as granting a license to any other intellectual
7 * property including but not limited to intellectual property relating
8 * to a hardware implementation of the functionality of the software

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724 TheISA::PCState pcState = thread->pcState();
725 bool needToFetch = !isRomMicroPC(pcState.microPC()) && !curMacroStaticInst;
726
727 if (needToFetch) {
728 _status = Running;
729 Request *ifetch_req = new Request();
730 ifetch_req->setThreadContext(_cpuId, /* thread ID */ 0);
731 setupFetchRequest(ifetch_req);
732 thread->itb->translateTiming(ifetch_req, tc, &fetchTranslation,
733 BaseTLB::Execute);
734 } else {
735 _status = IcacheWaitResponse;
736 completeIfetch(NULL);
737
738 numCycles += tickToCycles(curTick() - previousTick);
739 previousTick = curTick();
740 }
741}
742
743
744void
745TimingSimpleCPU::sendFetch(Fault fault, RequestPtr req, ThreadContext *tc)
746{
747 if (fault == NoFault) {
748 ifetch_pkt = new Packet(req, MemCmd::ReadReq, Packet::Broadcast);
749 ifetch_pkt->dataStatic(&inst);
750
751 if (!icachePort.sendTiming(ifetch_pkt)) {
752 // Need to wait for retry
753 _status = IcacheRetry;
754 } else {
755 // Need to wait for cache to respond
756 _status = IcacheWaitResponse;
757 // ownership of packet transferred to memory system
758 ifetch_pkt = NULL;
759 }
760 } else {
761 delete req;
762 // fetch fault: advance directly to next instruction (fault handler)
763 _status = Running;
764 advanceInst(fault);
765 }
766
767 numCycles += tickToCycles(curTick() - previousTick);
768 previousTick = curTick();

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795 fetch();
796 }
797}
798
799
800void
801TimingSimpleCPU::completeIfetch(PacketPtr pkt)
802{
803 // received a response from the icache: execute the received
804 // instruction
805
806 assert(!pkt || !pkt->isError());
807 assert(_status == IcacheWaitResponse);
808
809 _status = Running;
810

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876{
877 cpu->completeIfetch(pkt);
878}
879
880bool
881TimingSimpleCPU::IcachePort::recvTiming(PacketPtr pkt)
882{
883 if (pkt->isResponse() && !pkt->wasNacked()) {
884 // delay processing of returned data until next CPU clock edge
885 Tick next_tick = cpu->nextCycle(curTick());
886
887 if (next_tick == curTick())
888 cpu->completeIfetch(pkt);
889 else
890 tickEvent.schedule(pkt, next_tick);
891

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