1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 854 unchanged lines hidden (view full) ---

863}
864
865void
866TimingSimpleCPU::completeDataAccess(PacketPtr pkt)
867{
868 // received a response from the dcache: complete the load or store
869 // instruction
870 assert(!pkt->isError());
871
872 numCycles += tickToCycles(curTick - previousTick);
873 previousTick = curTick;
874
875 if (pkt->senderState) {
876 SplitFragmentSenderState * send_state =
877 dynamic_cast<SplitFragmentSenderState *>(pkt->senderState);
878 assert(send_state);

--- 13 unchanged lines hidden (view full) ---

892 return;
893 } else {
894 delete main_send_state;
895 big_pkt->senderState = NULL;
896 pkt = big_pkt;
897 }
898 }
899
900 assert(_status == DcacheWaitResponse || _status == DTBWaitResponse);
901 _status = Running;
902
903 Fault fault = curStaticInst->completeAcc(pkt, this, traceData);
904
905 // keep an instruction count
906 if (fault == NoFault)
907 countInst();
908 else if (traceData) {

--- 165 unchanged lines hidden ---