1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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427 BaseTLB::Mode mode = BaseTLB::Read;
428
429 RequestPtr req = new Request(asid, addr, data_size,
430 flags, pc, _cpuId, tid);
431
432 Addr split_addr = roundDown(addr + data_size - 1, block_size);
433 assert(split_addr <= addr || split_addr - addr < block_size);
434
435 _status = DTBWaitResponse;
436 if (split_addr > addr) {
437 RequestPtr req1, req2;
438 assert(!req->isLLSC() && !req->isSwap());
439 req->splitOnVaddr(split_addr, req1, req2);
440
441 WholeTranslationState *state =
442 new WholeTranslationState(req, req1, req2, (uint8_t *)(new T),

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456 thread->dtb->translateTiming(req, tc, translation, mode);
457 }
458
459 if (traceData) {
460 traceData->setData(data);
461 traceData->setAddr(addr);
462 }
463
464 // This will need a new way to tell if it has a dcache attached.
465 if (req->isUncacheable())
466 recordEvent("Uncached Read");
467
468 return NoFault;
469}
470
471#ifndef DOXYGEN_SHOULD_SKIP_THIS
472
473template
474Fault
475TimingSimpleCPU::read(Addr addr, Twin64_t &data, unsigned flags);

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505
506template<>
507Fault
508TimingSimpleCPU::read(Addr addr, float &data, unsigned flags)
509{
510 return read(addr, *(uint32_t*)&data, flags);
511}
512
513
514template<>
515Fault
516TimingSimpleCPU::read(Addr addr, int32_t &data, unsigned flags)
517{
518 return read(addr, (uint32_t&)data, flags);
519}
520
521bool

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550 BaseTLB::Mode mode = BaseTLB::Write;
551
552 RequestPtr req = new Request(asid, addr, data_size,
553 flags, pc, _cpuId, tid);
554
555 Addr split_addr = roundDown(addr + data_size - 1, block_size);
556 assert(split_addr <= addr || split_addr - addr < block_size);
557
558 T *dataP = new T;
559 *dataP = TheISA::htog(data);
560 _status = DTBWaitResponse;
561 if (split_addr > addr) {
562 RequestPtr req1, req2;
563 assert(!req->isLLSC() && !req->isSwap());
564 req->splitOnVaddr(split_addr, req1, req2);
565

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581 thread->dtb->translateTiming(req, tc, translation, mode);
582 }
583
584 if (traceData) {
585 traceData->setAddr(req->getVaddr());
586 traceData->setData(data);
587 }
588
589 // This will need a new way to tell if it's hooked up to a cache or not.
590 if (req->isUncacheable())
591 recordEvent("Uncached Write");
592
593 // If the write needs to have a fault on the access, consider calling
594 // changeStatus() and changing it to "bad addr write" or something.
595 return NoFault;
596}
597
598
599#ifndef DOXYGEN_SHOULD_SKIP_THIS
600template

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