1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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236
237 // just change status to Idle... if status != Running,
238 // completeInst() will not initiate fetch of next instruction.
239
240 notIdleFraction--;
241 _status = Idle;
242}
243
244
245template <class T>
246Fault
247TimingSimpleCPU::read(Addr addr, T &data, unsigned flags)
248{
249 Request *req =
250 new Request(/* asid */ 0, addr, sizeof(T), flags, thread->readPC(),
251 _cpuId, /* thread ID */ 0);
252
253 if (traceData) {
254 traceData->setAddr(req->getVaddr());
255 }
256
257 // translate to physical address
258 Fault fault = thread->translateDataReadReq(req);
259
260 // Now do the access.
261 if (fault == NoFault) {
262 PacketPtr pkt =
263 new Packet(req,
264 (req->isLocked() ?
265 MemCmd::LoadLockedReq : MemCmd::ReadReq),
266 Packet::Broadcast);
267 pkt->dataDynamic<T>(new T);
268
269 if (req->isMmapedIpr()) {
270 Tick delay;
271 delay = TheISA::handleIprRead(thread->getTC(), pkt);
272 new IprEvent(pkt, this, nextCycle(curTick + delay));
273 _status = DcacheWaitResponse;
274 dcache_pkt = NULL;
275 } else if (!dcachePort.sendTiming(pkt)) {
276 _status = DcacheRetry;
277 dcache_pkt = pkt;
278 } else {
279 _status = DcacheWaitResponse;
280 // memory system takes ownership of packet
281 dcache_pkt = NULL;
282 }
283
284 // This will need a new way to tell if it has a dcache attached.
285 if (req->isUncacheable())
286 recordEvent("Uncached Read");
287 } else {
288 delete req;
289 }
290
291 if (traceData) {
292 traceData->setData(data);
293 }
294 return fault;
295}
296
297Fault
298TimingSimpleCPU::translateDataReadAddr(Addr vaddr, Addr &paddr,
299 int size, unsigned flags)
300{
301 Request *req =
302 new Request(0, vaddr, size, flags, thread->readPC(), _cpuId, 0);

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359
360template<>
361Fault
362TimingSimpleCPU::read(Addr addr, int32_t &data, unsigned flags)
363{
364 return read(addr, (uint32_t&)data, flags);
365}
366
367
368template <class T>
369Fault
370TimingSimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res)
371{
372 Request *req =
373 new Request(/* asid */ 0, addr, sizeof(T), flags, thread->readPC(),
374 _cpuId, /* thread ID */ 0);
375
376 if (traceData) {
377 traceData->setAddr(req->getVaddr());
378 }
379
380 // translate to physical address
381 Fault fault = thread->translateDataWriteReq(req);
382
383 // Now do the access.
384 if (fault == NoFault) {
385 MemCmd cmd = MemCmd::WriteReq; // default
386 bool do_access = true; // flag to suppress cache access
387
388 if (req->isLocked()) {
389 cmd = MemCmd::StoreCondReq;
390 do_access = TheISA::handleLockedWrite(thread, req);
391 } else if (req->isSwap()) {
392 cmd = MemCmd::SwapReq;
393 if (req->isCondSwap()) {
394 assert(res);
395 req->setExtraData(*res);
396 }
397 }
398
399 // Note: need to allocate dcache_pkt even if do_access is
400 // false, as it's used unconditionally to call completeAcc().
401 assert(dcache_pkt == NULL);
402 dcache_pkt = new Packet(req, cmd, Packet::Broadcast);
403 dcache_pkt->allocate();
404 dcache_pkt->set(data);
405
406 if (do_access) {
407 if (req->isMmapedIpr()) {
408 Tick delay;
409 dcache_pkt->set(htog(data));
410 delay = TheISA::handleIprWrite(thread->getTC(), dcache_pkt);
411 new IprEvent(dcache_pkt, this, nextCycle(curTick + delay));
412 _status = DcacheWaitResponse;
413 dcache_pkt = NULL;
414 } else if (!dcachePort.sendTiming(dcache_pkt)) {
415 _status = DcacheRetry;
416 } else {
417 _status = DcacheWaitResponse;
418 // memory system takes ownership of packet
419 dcache_pkt = NULL;
420 }
421 }
422 // This will need a new way to tell if it's hooked up to a cache or not.
423 if (req->isUncacheable())
424 recordEvent("Uncached Write");
425 } else {
426 delete req;
427 }
428
429 if (traceData) {
430 traceData->setData(data);
431 }
432
433 // If the write needs to have a fault on the access, consider calling
434 // changeStatus() and changing it to "bad addr write" or something.
435 return fault;
436}
437
438Fault
439TimingSimpleCPU::translateDataWriteAddr(Addr vaddr, Addr &paddr,
440 int size, unsigned flags)
441{
442 Request *req =
443 new Request(0, vaddr, size, flags, thread->readPC(), _cpuId, 0);

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716}
717
718void
719TimingSimpleCPU::completeDataAccess(PacketPtr pkt)
720{
721 // received a response from the dcache: complete the load or store
722 // instruction
723 assert(!pkt->isError());
724 assert(_status == DcacheWaitResponse);
725 _status = Running;
726
727 numCycles += tickToCycles(curTick - previousTick);
728 previousTick = curTick;
729
730 Fault fault = curStaticInst->completeAcc(pkt, this, traceData);
731
732 // keep an instruction count
733 if (fault == NoFault)
734 countInst();
735 else if (traceData) {
736 // If there was a fault, we shouldn't trace this instruction.
737 delete traceData;

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782
783bool
784TimingSimpleCPU::DcachePort::recvTiming(PacketPtr pkt)
785{
786 if (pkt->isResponse() && !pkt->wasNacked()) {
787 // delay processing of returned data until next CPU clock edge
788 Tick next_tick = cpu->nextCycle(curTick);
789
790 if (next_tick == curTick)
791 cpu->completeDataAccess(pkt);
792 else
793 tickEvent.schedule(pkt, next_tick);
794
795 return true;
796 }
797 else if (pkt->wasNacked()) {
798 assert(cpu->_status == DcacheWaitResponse);
799 pkt->reinitNacked();
800 if (!sendTiming(pkt)) {
801 cpu->_status = DcacheRetry;

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815void
816TimingSimpleCPU::DcachePort::recvRetry()
817{
818 // we shouldn't get a retry unless we have a packet that we're
819 // waiting to transmit
820 assert(cpu->dcache_pkt != NULL);
821 assert(cpu->_status == DcacheRetry);
822 PacketPtr tmp = cpu->dcache_pkt;
823 if (sendTiming(tmp)) {
824 cpu->_status = DcacheWaitResponse;
825 // memory system takes ownership of packet
826 cpu->dcache_pkt = NULL;
827 }
828}
829
830TimingSimpleCPU::IprEvent::IprEvent(Packet *_pkt, TimingSimpleCPU *_cpu,
831 Tick t)

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