1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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526{
527 DPRINTF(SimpleCPU, "Fetch\n");
528
529 if (!curStaticInst || !curStaticInst->isDelayedCommit())
530 checkForInterrupts();
531
532 checkPcEventQueue();
533
534 Request *ifetch_req = new Request();
535 ifetch_req->setThreadContext(cpuId, /* thread ID */ 0);
536 Fault fault = setupFetchRequest(ifetch_req);
537
538 ifetch_pkt = new Packet(ifetch_req, MemCmd::ReadReq, Packet::Broadcast);
539 ifetch_pkt->dataStatic(&inst);
540
541 if (fault == NoFault) {
542 if (!icachePort.sendTiming(ifetch_pkt)) {
543 // Need to wait for retry
544 _status = IcacheRetry;
545 } else {
546 // Need to wait for cache to respond
547 _status = IcacheWaitResponse;
548 // ownership of packet transferred to memory system
549 ifetch_pkt = NULL;
550 }
551 } else {
552 delete ifetch_req;
553 delete ifetch_pkt;
554 // fetch fault: advance directly to next instruction (fault handler)
555 advanceInst(fault);
556 }
557
558 numCycles += tickToCycles(curTick - previousTick);
559 previousTick = curTick;
560}
561
562
563void

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576
577void
578TimingSimpleCPU::completeIfetch(PacketPtr pkt)
579{
580 DPRINTF(SimpleCPU, "Complete ICache Fetch\n");
581
582 // received a response from the icache: execute the received
583 // instruction
584 assert(!pkt->isError());
585 assert(_status == IcacheWaitResponse);
586
587 _status = Running;
588
589 numCycles += tickToCycles(curTick - previousTick);
590 previousTick = curTick;
591
592 if (getState() == SimObject::Draining) {
593 delete pkt->req;
594 delete pkt;
595
596 completeDrain();
597 return;
598 }
599
600 preExecute();
601 if (curStaticInst->isMemRef() && !curStaticInst->isDataPrefetch()) {
602 // load or store: just send to dcache

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653 postExecute();
654 // @todo remove me after debugging with legion done
655 if (curStaticInst && (!curStaticInst->isMicroop() ||
656 curStaticInst->isFirstMicroop()))
657 instCnt++;
658 advanceInst(fault);
659 }
660
661 delete pkt->req;
662 delete pkt;
663}
664
665void
666TimingSimpleCPU::IcachePort::ITickEvent::process()
667{
668 cpu->completeIfetch(pkt);
669}
670

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