1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

--- 279 unchanged lines hidden (view full) ---

288 recordEvent("Uncached Read");
289 } else {
290 delete req;
291 }
292
293 return fault;
294}
295
296#ifndef DOXYGEN_SHOULD_SKIP_THIS
297
298template
299Fault
300TimingSimpleCPU::read(Addr addr, Twin64_t &data, unsigned flags);
301
302template
303Fault

--- 102 unchanged lines hidden (view full) ---

406 }
407
408
409 // If the write needs to have a fault on the access, consider calling
410 // changeStatus() and changing it to "bad addr write" or something.
411 return fault;
412}
413
414
415#ifndef DOXYGEN_SHOULD_SKIP_THIS
416template
417Fault
418TimingSimpleCPU::write(Twin32_t data, Addr addr,
419 unsigned flags, uint64_t *res);
420
421template
422Fault

--- 392 unchanged lines hidden ---