1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Steve Reinhardt
29 */
30
31#include "arch/locked_mem.hh"
32#include "arch/utility.hh"
33#include "base/bigint.hh"
34#include "cpu/exetrace.hh"
35#include "cpu/simple/timing.hh"
36#include "mem/packet.hh"
37#include "mem/packet_access.hh"
38#include "params/TimingSimpleCPU.hh"
39#include "sim/system.hh"

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261 if (fault == NoFault) {
262 PacketPtr pkt =
263 new Packet(req,
264 (req->isLocked() ?
265 MemCmd::LoadLockedReq : MemCmd::ReadReq),
266 Packet::Broadcast);
267 pkt->dataDynamic<T>(new T);
268
269 if (!dcachePort.sendTiming(pkt)) {
270 _status = DcacheRetry;
271 dcache_pkt = pkt;
272 } else {
273 _status = DcacheWaitResponse;
274 // memory system takes ownership of packet
275 dcache_pkt = NULL;
276 }
277

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370 // Note: need to allocate dcache_pkt even if do_access is
371 // false, as it's used unconditionally to call completeAcc().
372 assert(dcache_pkt == NULL);
373 dcache_pkt = new Packet(req, cmd, Packet::Broadcast);
374 dcache_pkt->allocate();
375 dcache_pkt->set(data);
376
377 if (do_access) {
378 if (!dcachePort.sendTiming(dcache_pkt)) {
379 _status = DcacheRetry;
380 } else {
381 _status = DcacheWaitResponse;
382 // memory system takes ownership of packet
383 dcache_pkt = NULL;
384 }
385 }
386 // This will need a new way to tell if it's hooked up to a cache or not.

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546 countInst();
547 } else if (traceData) {
548 // If there was a fault, we shouldn't trace this instruction.
549 delete traceData;
550 traceData = NULL;
551 }
552
553 postExecute();
554 advanceInst(fault);
555 }
556 } else {
557 // non-memory instruction: execute completely now
558 Fault fault = curStaticInst->execute(this, traceData);
559
560 // keep an instruction count
561 if (fault == NoFault)
562 countInst();
563 else if (traceData) {
564 // If there was a fault, we shouldn't trace this instruction.
565 delete traceData;
566 traceData = NULL;
567 }
568
569 postExecute();
570 advanceInst(fault);
571 }
572
573 delete pkt->req;
574 delete pkt;
575}
576
577void

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725 PacketPtr tmp = cpu->dcache_pkt;
726 if (sendTiming(tmp)) {
727 cpu->_status = DcacheWaitResponse;
728 // memory system takes ownership of packet
729 cpu->dcache_pkt = NULL;
730 }
731}
732
733
734////////////////////////////////////////////////////////////////////////
735//
736// TimingSimpleCPU Simulation Object
737//
738TimingSimpleCPU *
739TimingSimpleCPUParams::create()
740{
741 TimingSimpleCPU::Params *params = new TimingSimpleCPU::Params();

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