1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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569
570 if (next_tick == curTick)
571 cpu->completeIfetch(pkt);
572 else
573 tickEvent.schedule(pkt, next_tick);
574
575 return true;
576 }
577 else {
578 //Snooping a Coherence Request, do nothing
579 return true;
580 }
581}
582
583void
584TimingSimpleCPU::IcachePort::recvRetry()
585{
586 // we shouldn't get a retry unless we have a packet that we're
587 // waiting to transmit
588 assert(cpu->ifetch_pkt != NULL);

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658
659 if (next_tick == curTick)
660 cpu->completeDataAccess(pkt);
661 else
662 tickEvent.schedule(pkt, next_tick);
663
664 return true;
665 }
666 else {
667 //Snooping a coherence req, do nothing
668 return true;
669 }
670}
671
672void
673TimingSimpleCPU::DcachePort::DTickEvent::process()
674{
675 cpu->completeDataAccess(pkt);
676}
677

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