1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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54void
55TimingSimpleCPU::init()
56{
57 BaseCPU::init();
58#if FULL_SYSTEM
59 for (int i = 0; i < threadContexts.size(); ++i) {
60 ThreadContext *tc = threadContexts[i];
61
62 // initialize the mem pointers
63 tc->init();
64
65 // initialize CPU, including PC
66 TheISA::initCPU(tc, tc->readCpuId());
67 }
68#endif
69}
70
71Tick
72TimingSimpleCPU::CpuPort::recvAtomic(PacketPtr pkt)

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236{
237 assert(thread_num == 0);
238 assert(thread);
239
240 assert(_status == Idle);
241
242 notIdleFraction++;
243 _status = Running;
244 // kick things off by initiating the fetch of the next instruction
245 fetchEvent =
246 new EventWrapper<TimingSimpleCPU, &TimingSimpleCPU::fetch>(this, false);
247 fetchEvent->schedule(nextCycle(curTick + cycles(delay)));
248}
249
250
251void

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