1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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527 cpu->completeIfetch(pkt);
528}
529
530bool
531TimingSimpleCPU::IcachePort::recvTiming(PacketPtr pkt)
532{
533 if (pkt->isResponse()) {
534 // delay processing of returned data until next CPU clock edge
535 Tick time = pkt->req->getTime();
536 while (time < curTick)
537 time += lat;
538
539 if (time == curTick)
540 cpu->completeIfetch(pkt);
541 else
542 tickEvent.schedule(pkt, time);
543
544 return true;
545 }
546 else {
547 //Snooping a Coherence Request, do nothing
548 return true;
549 }
550}

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605 drainEvent->process();
606}
607
608bool
609TimingSimpleCPU::DcachePort::recvTiming(PacketPtr pkt)
610{
611 if (pkt->isResponse()) {
612 // delay processing of returned data until next CPU clock edge
613 Tick time = pkt->req->getTime();
614 while (time < curTick)
615 time += lat;
616
617 if (time == curTick)
618 cpu->completeDataAccess(pkt);
619 else
620 tickEvent.schedule(pkt, time);
621
622 return true;
623 }
624 else {
625 //Snooping a coherence req, do nothing
626 return true;
627 }
628}

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