1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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523TimingSimpleCPU::IcachePort::ITickEvent::process()
524{
525 cpu->completeIfetch(pkt);
526}
527
528bool
529TimingSimpleCPU::IcachePort::recvTiming(Packet *pkt)
530{
531 // delay processing of returned data until next CPU clock edge
532 Tick time = pkt->req->getTime();
533 while (time < curTick)
534 time += lat;
535
536 if (time == curTick)
537 cpu->completeIfetch(pkt);
538 else
539 tickEvent.schedule(pkt, time);
540
541 return true;
542}
543
544void
545TimingSimpleCPU::IcachePort::recvRetry()
546{
547 // we shouldn't get a retry unless we have a packet that we're
548 // waiting to transmit
549 assert(cpu->ifetch_pkt != NULL);

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595 DPRINTF(Config, "Done draining\n");
596 changeState(SimObject::Drained);
597 drainEvent->process();
598}
599
600bool
601TimingSimpleCPU::DcachePort::recvTiming(Packet *pkt)
602{
603 // delay processing of returned data until next CPU clock edge
604 Tick time = pkt->req->getTime();
605 while (time < curTick)
606 time += lat;
607
608 if (time == curTick)
609 cpu->completeDataAccess(pkt);
610 else
611 tickEvent.schedule(pkt, time);
612
613 return true;
614}
615
616void
617TimingSimpleCPU::DcachePort::DTickEvent::process()
618{
619 cpu->completeDataAccess(pkt);
620}
621

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