1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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186 for (int i = 0; i < threadContexts.size(); ++i) {
187 ThreadContext *tc = threadContexts[i];
188 if (tc->status() == ThreadContext::Active && _status != Running) {
189 _status = Running;
190 break;
191 }
192 }
193
194 Port *peer;
195 if (icachePort.getPeer() == NULL) {
196 peer = oldCPU->getPort("icachePort")->getPeer();
197 icachePort.setPeer(peer);
198 } else {
199 peer = icachePort.getPeer();
200 }
201 peer->setPeer(&icachePort);
202
203 if (dcachePort.getPeer() == NULL) {
204 peer = oldCPU->getPort("dcachePort")->getPeer();
205 dcachePort.setPeer(peer);
206 } else {
207 peer = dcachePort.getPeer();
208 }
209 peer->setPeer(&dcachePort);
210}
211
212

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540 // instruction
541 assert(pkt->result == Packet::Success);
542 assert(_status == DcacheWaitResponse);
543 _status = Running;
544
545 numCycles += curTick - previousTick;
546 previousTick = curTick;
547
548 if (getState() == SimObject::Draining) {
549 completeDrain();
550
551 delete pkt->req;
552 delete pkt;
553
554 return;
555 }
556
557 Fault fault = curStaticInst->completeAcc(pkt, this, traceData);
558
559 delete pkt->req;
560 delete pkt;
561
562 postExecute();
563 advanceInst(fault);
564}
565
566
567void
568TimingSimpleCPU::completeDrain()
569{
570 DPRINTF(Config, "Done draining\n");

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