1/*
2 * Copyright (c) 2002-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;

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141 return 1;
142 }
143}
144
145void
146TimingSimpleCPU::resume()
147{
148 if (_status != SwitchedOut && _status != Idle) {
149 // Delete the old event if it existed.
150 if (fetchEvent) {
151 if (fetchEvent->scheduled())
152 fetchEvent->deschedule();
153
154 delete fetchEvent;
155 }
156
157 fetchEvent =
158 new EventWrapper<TimingSimpleCPU, &TimingSimpleCPU::fetch>(this, false);
159 fetchEvent->schedule(curTick);
160 }
161
162 assert(system->getMemoryMode() == System::Timing);
163 changeState(SimObject::Running);
164}
165
166void
167TimingSimpleCPU::switchOut()
168{
169 assert(status() == Running || status() == Idle);
170 _status = SwitchedOut;

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185 // running and schedule its tick event.
186 for (int i = 0; i < threadContexts.size(); ++i) {
187 ThreadContext *tc = threadContexts[i];
188 if (tc->status() == ThreadContext::Active && _status != Running) {
189 _status = Running;
190 break;
191 }
192 }
193}
194
195
196void
197TimingSimpleCPU::activateContext(int thread_num, int delay)
198{
199 assert(thread_num == 0);
200 assert(thread);

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528TimingSimpleCPU::completeDataAccess(Packet *pkt)
529{
530 // received a response from the dcache: complete the load or store
531 // instruction
532 assert(pkt->result == Packet::Success);
533 assert(_status == DcacheWaitResponse);
534 _status = Running;
535
536 if (getState() == SimObject::Draining) {
537 completeDrain();
538
539 delete pkt->req;
540 delete pkt;
541
542 return;
543 }
544
545 Fault fault = curStaticInst->completeAcc(pkt, this, traceData);
546
547 if (pkt->isRead() && pkt->req->isLocked()) {
548 TheISA::handleLockedRead(thread, pkt->req);
549 }
550
551 delete pkt->req;
552 delete pkt;
553
554 postExecute();
555 advanceInst(fault);
556}
557
558
559void
560TimingSimpleCPU::completeDrain()
561{

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